文件名称:rs232_UART
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失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
RS232通讯程序，已经调试通过，可以直接使用。-RS232 communication program, has been through debugging, can be used directly.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART\UART.prj
....\UART.prj.convert.7.3.bak
....\viewdraw\viewdraw.ini
....\........\.f\project.lst
....\synthesis\.recordref
....\.........\stdout.log
....\.........\traplog.tlg
....\.........\uart_test.areasrr
....\.........\uart_test.edn
....\.........\uart_test.fse
....\.........\uart_test.map
....\.........\uart_test.sdf
....\.........\uart_test.srd
....\.........\uart_test.srm
....\.........\uart_test.srr
....\.........\uart_test.srs
....\.........\uart_test.tlg
....\.........\uart_test_sdc.sdc
....\.........\uart_test_syn.prd
....\.........\uart_test_syn.prj
....\.........\syntmp\sap.log
....\.........\......\uart_test.msg
....\.........\......\uart_test.plg
....\.martgen\smartgen.aws
....\.imulation\meminit.dat
....\..........\modelsim.ini
....\..........\modelsim.ini.sav
....\hdl\rec.v
....\...\send.v
....\...\uart_test.v
....\designer\impl1\designer.log
....\........\.....\uart_test.adb
....\........\.....\uart_test.ide_des
....\........\.....\uart_test.stp
....\........\.....\uart_test.tcl
....\........\.....\..........dtf\verify.log
....\........\.....\uart_test.dtf
....\........\.....\simulation
....\viewdraw\wir
....\........\vf
....\........\sym
....\........\sch
....\synthesis\syntmp
....\designer\impl1
....\viewdraw
....\synthesis
....\stimulus
....\smartgen
....\simulation
....\phy_synthesis
....\hdl
....\designer
....\coreconsole
....\constraint
....\component
UART
rs232_UART\UART\designer\impl1\designer.log
..........\....\........\.....\uart_test.adb
..........\....\........\.....\..........dtf\verify.log
..........\....\........\.....\uart_test.ide_des
..........\....\........\.....\uart_test.stp
..........\....\........\.....\uart_test.tcl
..........\....\hdl\rec.v
..........\....\...\send.v
..........\....\...\uart_test.v
..........\....\simulation\meminit.dat
..........\....\..........\modelsim.ini
..........\....\..........\modelsim.ini.sav
..........\....\.martgen\smartgen.aws
..........\....\.ynthesis\.recordref
..........\....\.........\stdout.log
..........\....\.........\.yntmp\sap.log
..........\....\.........\......\uart_test.msg
..........\....\.........\......\uart_test.plg
..........\....\.........\traplog.tlg
..........\....\.........\uart_test.areasrr
..........\....\.........\uart_test.edn
..........\....\.........\uart_test.fse
..........\....\.........\uart_test.map
..........\....\.........\uart_test.sdf
..........\....\.........\uart_test.srd
..........\....\.........\uart_test.srm
..........\....\.........\uart_test.srr
..........\....\.........\uart_test.srs
..........\....\.........\uart_test.tlg
..........\....\.........\uart_test_sdc.sdc
..........\....\.........\uart_test_syn.prd
..........\....\.........\uart_test_syn.prj
..........\....\UART.prj
..........\....\UART.prj.convert.7.3.bak
..........\....\viewdraw\vf\project.lst
..........\....\........\viewdraw.ini
..........\waveperl.log
..........\UART\designer\impl1\simulation
..........\....\........\.....\uart_test.dtf
..........\....\........\impl1
..........\....\synthesis\syntmp
..........\....\viewdraw\sch
..........\....\........\sym
..........\....\........\vf
....\UART.prj.convert.7.3.bak
....\viewdraw\viewdraw.ini
....\........\.f\project.lst
....\synthesis\.recordref
....\.........\stdout.log
....\.........\traplog.tlg
....\.........\uart_test.areasrr
....\.........\uart_test.edn
....\.........\uart_test.fse
....\.........\uart_test.map
....\.........\uart_test.sdf
....\.........\uart_test.srd
....\.........\uart_test.srm
....\.........\uart_test.srr
....\.........\uart_test.srs
....\.........\uart_test.tlg
....\.........\uart_test_sdc.sdc
....\.........\uart_test_syn.prd
....\.........\uart_test_syn.prj
....\.........\syntmp\sap.log
....\.........\......\uart_test.msg
....\.........\......\uart_test.plg
....\.martgen\smartgen.aws
....\.imulation\meminit.dat
....\..........\modelsim.ini
....\..........\modelsim.ini.sav
....\hdl\rec.v
....\...\send.v
....\...\uart_test.v
....\designer\impl1\designer.log
....\........\.....\uart_test.adb
....\........\.....\uart_test.ide_des
....\........\.....\uart_test.stp
....\........\.....\uart_test.tcl
....\........\.....\..........dtf\verify.log
....\........\.....\uart_test.dtf
....\........\.....\simulation
....\viewdraw\wir
....\........\vf
....\........\sym
....\........\sch
....\synthesis\syntmp
....\designer\impl1
....\viewdraw
....\synthesis
....\stimulus
....\smartgen
....\simulation
....\phy_synthesis
....\hdl
....\designer
....\coreconsole
....\constraint
....\component
UART
rs232_UART\UART\designer\impl1\designer.log
..........\....\........\.....\uart_test.adb
..........\....\........\.....\..........dtf\verify.log
..........\....\........\.....\uart_test.ide_des
..........\....\........\.....\uart_test.stp
..........\....\........\.....\uart_test.tcl
..........\....\hdl\rec.v
..........\....\...\send.v
..........\....\...\uart_test.v
..........\....\simulation\meminit.dat
..........\....\..........\modelsim.ini
..........\....\..........\modelsim.ini.sav
..........\....\.martgen\smartgen.aws
..........\....\.ynthesis\.recordref
..........\....\.........\stdout.log
..........\....\.........\.yntmp\sap.log
..........\....\.........\......\uart_test.msg
..........\....\.........\......\uart_test.plg
..........\....\.........\traplog.tlg
..........\....\.........\uart_test.areasrr
..........\....\.........\uart_test.edn
..........\....\.........\uart_test.fse
..........\....\.........\uart_test.map
..........\....\.........\uart_test.sdf
..........\....\.........\uart_test.srd
..........\....\.........\uart_test.srm
..........\....\.........\uart_test.srr
..........\....\.........\uart_test.srs
..........\....\.........\uart_test.tlg
..........\....\.........\uart_test_sdc.sdc
..........\....\.........\uart_test_syn.prd
..........\....\.........\uart_test_syn.prj
..........\....\UART.prj
..........\....\UART.prj.convert.7.3.bak
..........\....\viewdraw\vf\project.lst
..........\....\........\viewdraw.ini
..........\waveperl.log
..........\UART\designer\impl1\simulation
..........\....\........\.....\uart_test.dtf
..........\....\........\impl1
..........\....\synthesis\syntmp
..........\....\viewdraw\sch
..........\....\........\sym
..........\....\........\vf