文件名称:UART
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
RS232实验例程2009年调试通过，请交流-RS232 test routine debugging through 2009, please communicate
(系统自动生成,下载前可以参看下载内容)
下载文件列表
UART\UART.prj
....\UART.prj.convert.7.3.bak
....\viewdraw\viewdraw.ini
....\........\.f\project.lst
....\synthesis\.recordref
....\.........\stdout.log
....\.........\traplog.tlg
....\.........\uart_test.areasrr
....\.........\uart_test.edn
....\.........\uart_test.fse
....\.........\uart_test.map
....\.........\uart_test.sdf
....\.........\uart_test.srd
....\.........\uart_test.srm
....\.........\uart_test.srr
....\.........\uart_test.srs
....\.........\uart_test.tlg
....\.........\uart_test_sdc.sdc
....\.........\uart_test_syn.prd
....\.........\uart_test_syn.prj
....\.........\syntmp\sap.log
....\.........\......\uart_test.msg
....\.........\......\uart_test.plg
....\.martgen\smartgen.aws
....\.imulation\meminit.dat
....\..........\modelsim.ini
....\..........\modelsim.ini.sav
....\hdl\rec.v
....\...\send.v
....\...\uart_test.v
....\designer\impl1\designer.log
....\........\.....\uart_test.adb
....\........\.....\uart_test.ide_des
....\........\.....\uart_test.stp
....\........\.....\uart_test.tcl
....\........\.....\..........dtf\verify.log
....\........\.....\uart_test.dtf
....\........\.....\simulation
....\viewdraw\wir
....\........\vf
....\........\sym
....\........\sch
....\synthesis\syntmp
....\designer\impl1
....\viewdraw
....\synthesis
....\stimulus
....\smartgen
....\simulation
....\phy_synthesis
....\hdl
....\designer
....\coreconsole
....\constraint
....\component
UART
....\UART.prj.convert.7.3.bak
....\viewdraw\viewdraw.ini
....\........\.f\project.lst
....\synthesis\.recordref
....\.........\stdout.log
....\.........\traplog.tlg
....\.........\uart_test.areasrr
....\.........\uart_test.edn
....\.........\uart_test.fse
....\.........\uart_test.map
....\.........\uart_test.sdf
....\.........\uart_test.srd
....\.........\uart_test.srm
....\.........\uart_test.srr
....\.........\uart_test.srs
....\.........\uart_test.tlg
....\.........\uart_test_sdc.sdc
....\.........\uart_test_syn.prd
....\.........\uart_test_syn.prj
....\.........\syntmp\sap.log
....\.........\......\uart_test.msg
....\.........\......\uart_test.plg
....\.martgen\smartgen.aws
....\.imulation\meminit.dat
....\..........\modelsim.ini
....\..........\modelsim.ini.sav
....\hdl\rec.v
....\...\send.v
....\...\uart_test.v
....\designer\impl1\designer.log
....\........\.....\uart_test.adb
....\........\.....\uart_test.ide_des
....\........\.....\uart_test.stp
....\........\.....\uart_test.tcl
....\........\.....\..........dtf\verify.log
....\........\.....\uart_test.dtf
....\........\.....\simulation
....\viewdraw\wir
....\........\vf
....\........\sym
....\........\sch
....\synthesis\syntmp
....\designer\impl1
....\viewdraw
....\synthesis
....\stimulus
....\smartgen
....\simulation
....\phy_synthesis
....\hdl
....\designer
....\coreconsole
....\constraint
....\component
UART