文件名称:AD[TLC549]
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进阶实验之AD[TLC549] 采集模拟输入，电压动态显示在数码管，由verilog编写-Advanced experiments AD [TLC549] capture analog input voltage is dynamically displayed on the LED, written by the verilog
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进阶实验_15_AD[TLC549] ：采集模拟输入，电压动态显示在数码管
.............................................................\Modelsim
.............................................................\........\ADC.cr.mti
.............................................................\........\ADC.mpf
.............................................................\........\sim.do
.............................................................\........\vsim.wlf
.............................................................\........\work
.............................................................\........\....\@a@d@c_549_@c@t@l
.............................................................\........\....\.................\verilog.asm
.............................................................\........\....\.................\_primary.dat
.............................................................\........\....\.................\_primary.vhd
.............................................................\........\....\@a@d@c_549_@c@t@l_tb
.............................................................\........\....\....................\verilog.asm
.............................................................\........\....\....................\_primary.dat
.............................................................\........\....\....................\_primary.vhd
.............................................................\........\....\_info
.............................................................\........\....\_temp
.............................................................\Quartus
.............................................................\.......\ADC_2_SEQ.asm.rpt
.............................................................\.......\ADC_2_SEQ.done
.............................................................\.......\ADC_2_SEQ.dpf
.............................................................\.......\ADC_2_SEQ.fit.rpt
.............................................................\.......\ADC_2_SEQ.fit.smsg
.............................................................\.......\ADC_2_SEQ.fit.summary
.............................................................\.......\ADC_2_SEQ.flow.rpt
.............................................................\.......\ADC_2_SEQ.map.rpt
.............................................................\.......\ADC_2_SEQ.map.summary
.............................................................\.......\ADC_2_SEQ.pin
.............................................................\.......\ADC_2_SEQ.pof
.............................................................\.......\ADC_2_SEQ.qpf
.............................................................\.......\ADC_2_SEQ.qsf
.............................................................\.......\ADC_2_SEQ.qws
.............................................................\.......\ADC_2_SEQ.sof
.............................................................\.......\ADC_2_SEQ.tan.rpt
.............................................................\.......\ADC_2_SEQ.tan.summary
.............................................................\.......\ADC_2_SEQ_assignment_defaults.qdf
.............................................................\.......\db
.............................................................\.......\..\ADC_2_SEQ.db_info
.............................................................\.......\..\ADC_2_SEQ.eco.cdb
.............................................................\.......\..\ADC_2_SEQ.sld_design_entry.sci
.............................................................\.......\..\ADC_2_SEQ_global_asgn_op.abo
.............................................................\.......\..\prev_cmp_ADC_2_SEQ.map.qmsg
.............................................................\.......\..\prev_cmp_ADC_2_SEQ.qmsg
.............................................................\.......\incremental_db
.............................................................\.......\..............\compiled_partitions
.............................................................\
.............................................................\Modelsim
.............................................................\........\ADC.cr.mti
.............................................................\........\ADC.mpf
.............................................................\........\sim.do
.............................................................\........\vsim.wlf
.............................................................\........\work
.............................................................\........\....\@a@d@c_549_@c@t@l
.............................................................\........\....\.................\verilog.asm
.............................................................\........\....\.................\_primary.dat
.............................................................\........\....\.................\_primary.vhd
.............................................................\........\....\@a@d@c_549_@c@t@l_tb
.............................................................\........\....\....................\verilog.asm
.............................................................\........\....\....................\_primary.dat
.............................................................\........\....\....................\_primary.vhd
.............................................................\........\....\_info
.............................................................\........\....\_temp
.............................................................\Quartus
.............................................................\.......\ADC_2_SEQ.asm.rpt
.............................................................\.......\ADC_2_SEQ.done
.............................................................\.......\ADC_2_SEQ.dpf
.............................................................\.......\ADC_2_SEQ.fit.rpt
.............................................................\.......\ADC_2_SEQ.fit.smsg
.............................................................\.......\ADC_2_SEQ.fit.summary
.............................................................\.......\ADC_2_SEQ.flow.rpt
.............................................................\.......\ADC_2_SEQ.map.rpt
.............................................................\.......\ADC_2_SEQ.map.summary
.............................................................\.......\ADC_2_SEQ.pin
.............................................................\.......\ADC_2_SEQ.pof
.............................................................\.......\ADC_2_SEQ.qpf
.............................................................\.......\ADC_2_SEQ.qsf
.............................................................\.......\ADC_2_SEQ.qws
.............................................................\.......\ADC_2_SEQ.sof
.............................................................\.......\ADC_2_SEQ.tan.rpt
.............................................................\.......\ADC_2_SEQ.tan.summary
.............................................................\.......\ADC_2_SEQ_assignment_defaults.qdf
.............................................................\.......\db
.............................................................\.......\..\ADC_2_SEQ.db_info
.............................................................\.......\..\ADC_2_SEQ.eco.cdb
.............................................................\.......\..\ADC_2_SEQ.sld_design_entry.sci
.............................................................\.......\..\ADC_2_SEQ_global_asgn_op.abo
.............................................................\.......\..\prev_cmp_ADC_2_SEQ.map.qmsg
.............................................................\.......\..\prev_cmp_ADC_2_SEQ.qmsg
.............................................................\.......\incremental_db
.............................................................\.......\..............\compiled_partitions
.............................................................\