文件名称:clk_div2
介绍说明－－下载内容均来自于网络，请自行研究使用
本源码是分频器的VHDL,在QUARTUS2下已进行仿真和验证，-The source is the divider of the VHDL, have been carried out under the QUARTUS2 simulation and verification,
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clk_div2\clk_div2.asm.rpt
........\clk_div2.cdf
........\clk_div2.done
........\clk_div2.dpf
........\clk_div2.fit.rpt
........\clk_div2.fit.smsg
........\clk_div2.fit.summary
........\clk_div2.flow.rpt
........\clk_div2.map.rpt
........\clk_div2.map.summary
........\clk_div2.pin
........\clk_div2.pof
........\clk_div2.qpf
........\clk_div2.qsf
........\clk_div2.qws
........\clk_div2.sim.rpt
........\clk_div2.sof
........\clk_div2.tan.rpt
........\clk_div2.tan.summary
........\clk_div2.vhd
........\clk_div2.vhd.bak
........\clk_div2.vwf
........\db\add_sub_flh.tdf
........\..\clk_div2.analyze_file.qmsg
........\..\clk_div2.asm.qmsg
........\..\clk_div2.asm_labs.ddb
........\..\clk_div2.cbx.xml
........\..\clk_div2.cmp.cdb
........\..\clk_div2.cmp.hdb
........\..\clk_div2.cmp.logdb
........\..\clk_div2.cmp.rdb
........\..\clk_div2.cmp.tdb
........\..\clk_div2.cmp0.ddb
........\..\clk_div2.cmp2.ddb
........\..\clk_div2.db_info
........\..\clk_div2.eco.cdb
........\..\clk_div2.eds_overflow
........\..\clk_div2.fit.qmsg
........\..\clk_div2.fnsim.hdb
........\..\clk_div2.fnsim.qmsg
........\..\clk_div2.hier_info
........\..\clk_div2.hif
........\..\clk_div2.map.cdb
........\..\clk_div2.map.hdb
........\..\clk_div2.map.logdb
........\..\clk_div2.map.qmsg
........\..\clk_div2.pre_map.cdb
........\..\clk_div2.pre_map.hdb
........\..\clk_div2.rtlv.hdb
........\..\clk_div2.rtlv_sg.cdb
........\..\clk_div2.rtlv_sg_swap.cdb
........\..\clk_div2.sgdiff.cdb
........\..\clk_div2.sgdiff.hdb
........\..\clk_div2.signalprobe.cdb
........\..\clk_div2.sim.cvwf
........\..\clk_div2.sim.hdb
........\..\clk_div2.sim.qmsg
........\..\clk_div2.sim.rdb
........\..\clk_div2.simfam
........\..\clk_div2.sld_design_entry.sci
........\..\clk_div2.sld_design_entry_dsc.sci
........\..\clk_div2.syn_hier_info
........\..\clk_div2.tan.qmsg
........\..\clk_div2.tis_db_list.ddb
........\..\clk_div2.tmw_info
........\..\prev_cmp_clk_div2.asm.qmsg
........\..\prev_cmp_clk_div2.fit.qmsg
........\..\prev_cmp_clk_div2.map.qmsg
........\..\prev_cmp_clk_div2.qmsg
........\..\prev_cmp_clk_div2.sim.qmsg
........\..\prev_cmp_clk_div2.tan.qmsg
........\..\wed.wsf
........\db
clk_div2
........\clk_div2.cdf
........\clk_div2.done
........\clk_div2.dpf
........\clk_div2.fit.rpt
........\clk_div2.fit.smsg
........\clk_div2.fit.summary
........\clk_div2.flow.rpt
........\clk_div2.map.rpt
........\clk_div2.map.summary
........\clk_div2.pin
........\clk_div2.pof
........\clk_div2.qpf
........\clk_div2.qsf
........\clk_div2.qws
........\clk_div2.sim.rpt
........\clk_div2.sof
........\clk_div2.tan.rpt
........\clk_div2.tan.summary
........\clk_div2.vhd
........\clk_div2.vhd.bak
........\clk_div2.vwf
........\db\add_sub_flh.tdf
........\..\clk_div2.analyze_file.qmsg
........\..\clk_div2.asm.qmsg
........\..\clk_div2.asm_labs.ddb
........\..\clk_div2.cbx.xml
........\..\clk_div2.cmp.cdb
........\..\clk_div2.cmp.hdb
........\..\clk_div2.cmp.logdb
........\..\clk_div2.cmp.rdb
........\..\clk_div2.cmp.tdb
........\..\clk_div2.cmp0.ddb
........\..\clk_div2.cmp2.ddb
........\..\clk_div2.db_info
........\..\clk_div2.eco.cdb
........\..\clk_div2.eds_overflow
........\..\clk_div2.fit.qmsg
........\..\clk_div2.fnsim.hdb
........\..\clk_div2.fnsim.qmsg
........\..\clk_div2.hier_info
........\..\clk_div2.hif
........\..\clk_div2.map.cdb
........\..\clk_div2.map.hdb
........\..\clk_div2.map.logdb
........\..\clk_div2.map.qmsg
........\..\clk_div2.pre_map.cdb
........\..\clk_div2.pre_map.hdb
........\..\clk_div2.rtlv.hdb
........\..\clk_div2.rtlv_sg.cdb
........\..\clk_div2.rtlv_sg_swap.cdb
........\..\clk_div2.sgdiff.cdb
........\..\clk_div2.sgdiff.hdb
........\..\clk_div2.signalprobe.cdb
........\..\clk_div2.sim.cvwf
........\..\clk_div2.sim.hdb
........\..\clk_div2.sim.qmsg
........\..\clk_div2.sim.rdb
........\..\clk_div2.simfam
........\..\clk_div2.sld_design_entry.sci
........\..\clk_div2.sld_design_entry_dsc.sci
........\..\clk_div2.syn_hier_info
........\..\clk_div2.tan.qmsg
........\..\clk_div2.tis_db_list.ddb
........\..\clk_div2.tmw_info
........\..\prev_cmp_clk_div2.asm.qmsg
........\..\prev_cmp_clk_div2.fit.qmsg
........\..\prev_cmp_clk_div2.map.qmsg
........\..\prev_cmp_clk_div2.qmsg
........\..\prev_cmp_clk_div2.sim.qmsg
........\..\prev_cmp_clk_div2.tan.qmsg
........\..\wed.wsf
........\db
clk_div2