文件名称:alarm_machine
介绍说明－－下载内容均来自于网络，请自行研究使用
basic verilog HDL samples realizing an alarm clock circuit
(系统自动生成,下载前可以参看下载内容)
下载文件列表
alarm_machine\ALARMSM_2_TB.v
.............\ALARM_BLOCK.v
.............\ALARM_COUNTER.v
.............\ALARM_SM_2.v
.............\ALARM_STATE_MACHINE.v
.............\COMPARATOR.v
.............\CONVERTOR_CKT.v
.............\CONVERTOR_CKT_SUB.v
.............\CONVERTOR_CKT_TB.v
.............\CONVERTOR_DIGIT.v
.............\MUX.v
.............\run.f
.............\test.shm\test.dsn
.............\........\test.trn
.............\test.vcd
.............\TIMER_tb_v1.v
.............\TIME_BLOCK.v
.............\TIME_BLOCK_TB.v
.............\TIME_COUNTER.v
.............\TIME_STATE_MACHINE.v
.............\TOP.v
.............\verilog.log
.............\test.shm
alarm_machine
.............\ALARM_BLOCK.v
.............\ALARM_COUNTER.v
.............\ALARM_SM_2.v
.............\ALARM_STATE_MACHINE.v
.............\COMPARATOR.v
.............\CONVERTOR_CKT.v
.............\CONVERTOR_CKT_SUB.v
.............\CONVERTOR_CKT_TB.v
.............\CONVERTOR_DIGIT.v
.............\MUX.v
.............\run.f
.............\test.shm\test.dsn
.............\........\test.trn
.............\test.vcd
.............\TIMER_tb_v1.v
.............\TIME_BLOCK.v
.............\TIME_BLOCK_TB.v
.............\TIME_COUNTER.v
.............\TIME_STATE_MACHINE.v
.............\TOP.v
.............\verilog.log
.............\test.shm
alarm_machine