文件名称:velocity_Verilog
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速度表（velocity）要求：1．显示汽车Km/h数；2．车轮每转一圈，有一传感脉冲；每个脉冲代表1m的距离；3．采样周期设为10s；
4．要求显示到小数点后边两位；5．用数码管显示；6. 最高时速小于300Km/h。（约为83.3m/s）
-use verilog to realize velocity
4．要求显示到小数点后边两位；5．用数码管显示；6. 最高时速小于300Km/h。（约为83.3m/s）
-use verilog to realize velocity
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下载文件列表
汽车时速表的Verilog实现
.......................\velocity\velocity.txt
.......................\........\velocity.v
.......................\........\velocity.v.bak
.......................\........\velocity_prj.cr.mti
.......................\........\velocity_prj.mpf
.......................\........\velocity_testbench.txt
.......................\........\velocity_testbench.v
.......................\........\velocity_testbench.v.bak
.......................\........\vsim.wlf
.......................\........\work\velocity\verilog.asm
.......................\........\....\........\verilog.rw
.......................\........\....\........\_primary.dat
.......................\........\....\........\_primary.dbs
.......................\........\....\........\_primary.vhd
.......................\........\....\........_testbench\verilog.asm
.......................\........\....\..................\verilog.rw
.......................\........\....\..................\_primary.dat
.......................\........\....\..................\_primary.dbs
.......................\........\....\..................\_primary.vhd
.......................\........\....\_info
.......................\........\....\_vmake
.......................\........\速度表题目要求.doc
.......................\........\work\velocity
.......................\........\....\velocity_testbench
.......................\........\....\_temp
.......................\........\work
.......................\velocity
.......................\velocity\velocity.txt
.......................\........\velocity.v
.......................\........\velocity.v.bak
.......................\........\velocity_prj.cr.mti
.......................\........\velocity_prj.mpf
.......................\........\velocity_testbench.txt
.......................\........\velocity_testbench.v
.......................\........\velocity_testbench.v.bak
.......................\........\vsim.wlf
.......................\........\work\velocity\verilog.asm
.......................\........\....\........\verilog.rw
.......................\........\....\........\_primary.dat
.......................\........\....\........\_primary.dbs
.......................\........\....\........\_primary.vhd
.......................\........\....\........_testbench\verilog.asm
.......................\........\....\..................\verilog.rw
.......................\........\....\..................\_primary.dat
.......................\........\....\..................\_primary.dbs
.......................\........\....\..................\_primary.vhd
.......................\........\....\_info
.......................\........\....\_vmake
.......................\........\速度表题目要求.doc
.......................\........\work\velocity
.......................\........\....\velocity_testbench
.......................\........\....\_temp
.......................\........\work
.......................\velocity