文件名称:test_verilog
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog编程实践，内含多个实例，均已在modelsim下编译通过-a simulation
(系统自动生成,下载前可以参看下载内容)
下载文件列表
test_verilog\bijiao.cr.mti
............\bijiao.mpf
............\bijiao.v
............\bijiao.v.bak
............\blocking.v
............\blocking.v.bak
............\compare.cr.mti
............\compare.mpf
............\compare.v
............\compare.v.bak
............\nonblocking.v
............\nonblocking.v.bak
............\statemachine.cr.mti
............\statemachine.mpf
............\statemachine.v
............\statetestbench.v
............\test1.cr.mti
............\test1.mpf
............\test1.v
............\test1.v.bak
............\test1testbench.v
............\test1testbench.v.bak
............\test2.cr.mti
............\test2.mpf
............\test2.v
............\test2.v.bak
............\test2testbench.v
............\test2testbench.v.bak
............\test3.cr.mti
............\test3.mpf
............\test3.v
............\test3.v.bak
............\test3testbench.v
............\test3testbench.v.bak
............\test4.cr.mti
............\test4.mpf
............\test4.v
............\test4.v.bak
............\test4testbench.v
............\test4testbench.v.bak
............\test5.cr.mti
............\test5.mpf
............\test5.v
............\test5.v.bak
............\test5bench.v
............\test5bench.v.bak
............\testbench.v
............\testbench.v.bak
............\testbench4.v
............\testbench4.v.bak
............\testcompare.v
............\testcompare.v.bak
............\vish_stacktrace.vstf
............\vsim.wlf
............\work\bijiao\verilog.asm
............\....\......\_primary.dat
............\....\......\_primary.vhd
............\....\.locking\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\compare\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\half_clk\_primary.dat
............\....\........\_primary.vhd
............\....\nonblocking\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\test1\_primary.dat
............\....\.....\_primary.vhd
............\....\.....testbench\_primary.dat
............\....\..............\_primary.vhd
............\....\....2\verilog.asm
............\....\.....\_primary.dat
............\....\.....\_primary.vhd
............\....\.....testbench\_primary.dat
............\....\..............\_primary.vhd
............\....\....3\verilog.asm
............\....\.....\_primary.dat
............\....\.....\_primary.vhd
............\....\.....testbench\verilog.asm
............\....\..............\_primary.dat
............\....\..............\_primary.vhd
............\....\....5\verilog.asm
............\....\.....\_primary.dat
............\....\.....\_primary.vhd
............\....\.....bench\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\....bench\verilog.asm
............\....\.........\_primary.dat
............\....\.........\_primary.vhd
............\....\.........4\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\....compare\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\_info
............\zuse.cr.mti
............\bijiao.mpf
............\bijiao.v
............\bijiao.v.bak
............\blocking.v
............\blocking.v.bak
............\compare.cr.mti
............\compare.mpf
............\compare.v
............\compare.v.bak
............\nonblocking.v
............\nonblocking.v.bak
............\statemachine.cr.mti
............\statemachine.mpf
............\statemachine.v
............\statetestbench.v
............\test1.cr.mti
............\test1.mpf
............\test1.v
............\test1.v.bak
............\test1testbench.v
............\test1testbench.v.bak
............\test2.cr.mti
............\test2.mpf
............\test2.v
............\test2.v.bak
............\test2testbench.v
............\test2testbench.v.bak
............\test3.cr.mti
............\test3.mpf
............\test3.v
............\test3.v.bak
............\test3testbench.v
............\test3testbench.v.bak
............\test4.cr.mti
............\test4.mpf
............\test4.v
............\test4.v.bak
............\test4testbench.v
............\test4testbench.v.bak
............\test5.cr.mti
............\test5.mpf
............\test5.v
............\test5.v.bak
............\test5bench.v
............\test5bench.v.bak
............\testbench.v
............\testbench.v.bak
............\testbench4.v
............\testbench4.v.bak
............\testcompare.v
............\testcompare.v.bak
............\vish_stacktrace.vstf
............\vsim.wlf
............\work\bijiao\verilog.asm
............\....\......\_primary.dat
............\....\......\_primary.vhd
............\....\.locking\verilog.asm
............\....\........\_primary.dat
............\....\........\_primary.vhd
............\....\compare\verilog.asm
............\....\.......\_primary.dat
............\....\.......\_primary.vhd
............\....\half_clk\_primary.dat
............\....\........\_primary.vhd
............\....\nonblocking\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\test1\_primary.dat
............\....\.....\_primary.vhd
............\....\.....testbench\_primary.dat
............\....\..............\_primary.vhd
............\....\....2\verilog.asm
............\....\.....\_primary.dat
............\....\.....\_primary.vhd
............\....\.....testbench\_primary.dat
............\....\..............\_primary.vhd
............\....\....3\verilog.asm
............\....\.....\_primary.dat
............\....\.....\_primary.vhd
............\....\.....testbench\verilog.asm
............\....\..............\_primary.dat
............\....\..............\_primary.vhd
............\....\....5\verilog.asm
............\....\.....\_primary.dat
............\....\.....\_primary.vhd
............\....\.....bench\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\....bench\verilog.asm
............\....\.........\_primary.dat
............\....\.........\_primary.vhd
............\....\.........4\verilog.asm
............\....\..........\_primary.dat
............\....\..........\_primary.vhd
............\....\....compare\verilog.asm
............\....\...........\_primary.dat
............\....\...........\_primary.vhd
............\....\_info
............\zuse.cr.mti