文件名称:fft1

  • 所属分类:
  • VHDL编程
  • 资源属性:
  • [ASM] [源码]
  • 上传时间:
  • 2012-11-26
  • 文件大小:
  • 150kb
  • 下载次数:
  • 0次
  • 提 供 者:
  • h*
  • 相关连接:
  • 下载说明:
  • 别用迅雷下载,失败请重下,重下不扣分!

介绍说明--下载内容均来自于网络,请自行研究使用

fft processor code working code in verilog--fft processor code working code in verilog-VVV
(系统自动生成,下载前可以参看下载内容)

下载文件列表

fft1\bm.v

....\booth.v

....\butterfly.v

....\cl42_20.v

....\cla20.v

....\clk_div.v

....\complex_mul.v

....\control.v

....\csa_13.v

....\csa_15.v

....\dataout.v

....\delay1.v

....\delay16.v

....\delay2.v

....\delay4.v

....\delay8.v

....\dff.v

....\fft1.cr.mti

....\fft1.mpf

....\fft64.v

....\input_buffer.v

....\inverter.v

....\multiplier.v

....\opo2.v

....\opo3.v

....\opo4.v

....\result_out.txt

....\switch1.v

....\switch16.v

....\switch2.v

....\switch4.v

....\switch8.v

....\tbcla.v

....\tbmul.v

....\tb_fft64.v

....\tb_inputbuffer.v

....\twiddle1.v

....\vsim.wlf

....\work\bm\verilog.asm

....\....\..\_primary.dat

....\....\..\_primary.vhd

....\....\.ooth\verilog.asm

....\....\.....\_primary.dat

....\....\.....\_primary.vhd

....\....\.utterfly\verilog.asm

....\....\.........\_primary.dat

....\....\.........\_primary.vhd

....\....\cl42_20\verilog.asm

....\....\.......\_primary.dat

....\....\.......\_primary.vhd

....\....\..a20\verilog.asm

....\....\.....\_primary.dat

....\....\.....\_primary.vhd

....\....\..k_div\verilog.asm

....\....\.......\_primary.dat

....\....\.......\_primary.vhd

....\....\.omplex_mul\verilog.asm

....\....\...........\_primary.dat

....\....\...........\_primary.vhd

....\....\..ntrol\verilog.asm

....\....\.......\_primary.dat

....\....\.......\_primary.vhd

....\....\.sa_13\verilog.asm

....\....\......\_primary.dat

....\....\......\_primary.vhd

....\....\.....5\verilog.asm

....\....\......\_primary.dat

....\....\......\_primary.vhd

....\....\dataout\verilog.asm

....\....\.......\_primary.dat

....\....\.......\_primary.vhd

....\....\.elay1\verilog.asm

....\....\......\_primary.dat

....\....\......\_primary.vhd

....\....\......6\verilog.asm

....\....\.......\_primary.dat

....\....\.......\_primary.vhd

....\....\.....2\verilog.asm

....\....\......\_primary.dat

....\....\......\_primary.vhd

....\....\.....4\verilog.asm

....\....\......\_primary.dat

....\....\......\_primary.vhd

....\....\.....8\verilog.asm

....\....\......\_primary.dat

....\....\......\_primary.vhd

....\....\.ff\verilog.asm

....\....\...\_primary.dat

....\....\...\_primary.vhd

....\....\fft64\verilog.asm

....\....\.....\_primary.dat

....\....\.....\_primary.vhd

....\....\input_buffer\verilog.asm

....\....\............\_primary.dat

....\....\............\_primary.vhd

....\....\..verter\verilog.asm

....\....\........\_primary.dat

....\....\........\_primary.vhd

....\....\multiplier\verilog.asm

....\....\..........\_primary.dat

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