文件名称:ADigCLK
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介绍说明－－下载内容均来自于网络，请自行研究使用
用VHDL编写的一个数字钟。该模块是顶层模块，用VHDL例化语句例化各个子模块并组装成一个完整的数字钟。与我的其它8个模块配套构成一个数字钟。
-A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all submodules into a complete digital clock.It is one of my total 9 modules that are used to design a digital clock.
-A digital clock programmed with VHDL.This module is the top-level module, it utilizes the Component instantiation of VHDL to incorporate all submodules into a complete digital clock.It is one of my total 9 modules that are used to design a digital clock.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ADigCLK\ADigCLK.asm.rpt
.......\ADigCLK.done
.......\ADigCLK.fit.rpt
.......\ADigCLK.fit.summary
.......\ADigCLK.flow.rpt
.......\ADigCLK.jpg
.......\ADigCLK.map.rpt
.......\ADigCLK.map.summary
.......\ADigCLK.pin
.......\ADigCLK.pof
.......\ADigCLK.qpf
.......\ADigCLK.qsf
.......\ADigCLK.qws
.......\ADigCLK.tan.rpt
.......\ADigCLK.tan.summary
.......\ADigCLK.vhd
.......\ADigCLK.vhd.bak
.......\ADigCLK.vwf
.......\db\add_sub_3kh.tdf
.......\..\add_sub_bph.tdf
.......\..\add_sub_pnh.tdf
.......\..\ADigCLK.asm.qmsg
.......\..\ADigCLK.asm.rdb
.......\..\ADigCLK.cbx.xml
.......\..\ADigCLK.cmp.cdb
.......\..\ADigCLK.cmp.hdb
.......\..\ADigCLK.cmp.logdb
.......\..\ADigCLK.cmp.rdb
.......\..\ADigCLK.cmp.tdb
.......\..\ADigCLK.cmp0.ddb
.......\..\ADigCLK.db_info
.......\..\ADigCLK.eco.cdb
.......\..\ADigCLK.fit.qmsg
.......\..\ADigCLK.hier_info
.......\..\ADigCLK.hif
.......\..\ADigCLK.lpc.html
.......\..\ADigCLK.lpc.rdb
.......\..\ADigCLK.lpc.txt
.......\..\ADigCLK.map.cdb
.......\..\ADigCLK.map.hdb
.......\..\ADigCLK.map.logdb
.......\..\ADigCLK.map.qmsg
.......\..\ADigCLK.pre_map.cdb
.......\..\ADigCLK.pre_map.hdb
.......\..\ADigCLK.rpp.qmsg
.......\..\ADigCLK.rtlv.hdb
.......\..\ADigCLK.rtlv_sg.cdb
.......\..\ADigCLK.rtlv_sg_swap.cdb
.......\..\ADigCLK.sgate.rvd
.......\..\ADigCLK.sgate_sm.rvd
.......\..\ADigCLK.sgdiff.cdb
.......\..\ADigCLK.sgdiff.hdb
.......\..\ADigCLK.sim.hdb
.......\..\ADigCLK.sim.qmsg
.......\..\ADigCLK.sld_design_entry.sci
.......\..\ADigCLK.sld_design_entry_dsc.sci
.......\..\ADigCLK.smart_action.txt
.......\..\ADigCLK.syn_hier_info
.......\..\ADigCLK.tan.qmsg
.......\..\ADigCLK.tis_db_list.ddb
.......\..\ADigCLK.tmw_info
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_ADigCLK.asm.qmsg
.......\..\prev_cmp_ADigCLK.fit.qmsg
.......\..\prev_cmp_ADigCLK.map.qmsg
.......\..\prev_cmp_ADigCLK.qmsg
.......\..\prev_cmp_ADigCLK.tan.qmsg
.......\..\wed.wsf
.......\incremental_db\compiled_partitions\ADigCLK.root_partition.map.kpt
.......\..............\README
.......\..............\compiled_partitions
.......\db
.......\incremental_db
ADigCLK
.......\ADigCLK.done
.......\ADigCLK.fit.rpt
.......\ADigCLK.fit.summary
.......\ADigCLK.flow.rpt
.......\ADigCLK.jpg
.......\ADigCLK.map.rpt
.......\ADigCLK.map.summary
.......\ADigCLK.pin
.......\ADigCLK.pof
.......\ADigCLK.qpf
.......\ADigCLK.qsf
.......\ADigCLK.qws
.......\ADigCLK.tan.rpt
.......\ADigCLK.tan.summary
.......\ADigCLK.vhd
.......\ADigCLK.vhd.bak
.......\ADigCLK.vwf
.......\db\add_sub_3kh.tdf
.......\..\add_sub_bph.tdf
.......\..\add_sub_pnh.tdf
.......\..\ADigCLK.asm.qmsg
.......\..\ADigCLK.asm.rdb
.......\..\ADigCLK.cbx.xml
.......\..\ADigCLK.cmp.cdb
.......\..\ADigCLK.cmp.hdb
.......\..\ADigCLK.cmp.logdb
.......\..\ADigCLK.cmp.rdb
.......\..\ADigCLK.cmp.tdb
.......\..\ADigCLK.cmp0.ddb
.......\..\ADigCLK.db_info
.......\..\ADigCLK.eco.cdb
.......\..\ADigCLK.fit.qmsg
.......\..\ADigCLK.hier_info
.......\..\ADigCLK.hif
.......\..\ADigCLK.lpc.html
.......\..\ADigCLK.lpc.rdb
.......\..\ADigCLK.lpc.txt
.......\..\ADigCLK.map.cdb
.......\..\ADigCLK.map.hdb
.......\..\ADigCLK.map.logdb
.......\..\ADigCLK.map.qmsg
.......\..\ADigCLK.pre_map.cdb
.......\..\ADigCLK.pre_map.hdb
.......\..\ADigCLK.rpp.qmsg
.......\..\ADigCLK.rtlv.hdb
.......\..\ADigCLK.rtlv_sg.cdb
.......\..\ADigCLK.rtlv_sg_swap.cdb
.......\..\ADigCLK.sgate.rvd
.......\..\ADigCLK.sgate_sm.rvd
.......\..\ADigCLK.sgdiff.cdb
.......\..\ADigCLK.sgdiff.hdb
.......\..\ADigCLK.sim.hdb
.......\..\ADigCLK.sim.qmsg
.......\..\ADigCLK.sld_design_entry.sci
.......\..\ADigCLK.sld_design_entry_dsc.sci
.......\..\ADigCLK.smart_action.txt
.......\..\ADigCLK.syn_hier_info
.......\..\ADigCLK.tan.qmsg
.......\..\ADigCLK.tis_db_list.ddb
.......\..\ADigCLK.tmw_info
.......\..\logic_util_heursitic.dat
.......\..\prev_cmp_ADigCLK.asm.qmsg
.......\..\prev_cmp_ADigCLK.fit.qmsg
.......\..\prev_cmp_ADigCLK.map.qmsg
.......\..\prev_cmp_ADigCLK.qmsg
.......\..\prev_cmp_ADigCLK.tan.qmsg
.......\..\wed.wsf
.......\incremental_db\compiled_partitions\ADigCLK.root_partition.map.kpt
.......\..............\README
.......\..............\compiled_partitions
.......\db
.......\incremental_db
ADigCLK