文件名称:20070523232051339
- 所属分类：
- 单片机(51,AVR,MSP430等)
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 137kb
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- 0次
- 提 供 者：
- j*
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一个嵌入式RISC CPU的Verilog 设计源码\embedded_risc\CVS\Root
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....................................\.............\...\Entries.Old
....................................\.............\...\Entries
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....................................\.............\...\Entries.Extra
....................................\.............\SOC_Design.pdf
....................................\.............\Machine_Language\CVS\Root
....................................\.............\................\...\Repository
....................................\.............\................\...\Template
....................................\.............\................\...\Entries.Old
....................................\.............\................\...\Entries
....................................\.............\................\...\Entries.Extra.Old
....................................\.............\................\...\Entries.Extra
....................................\.............\................\program.txt
....................................\.............\Test_Bench_Verilog\CVS\Root
....................................\.............\..................\...\Repository
....................................\.............\..................\...\Template
....................................\.............\..................\...\Entries.Old
....................................\.............\..................\...\Entries
....................................\.............\..................\...\Entries.Extra.Old
....................................\.............\..................\...\Entries.Extra
....................................\.............\..................\Top_level_tb.tf
....................................\.............\Verilog\CVS\Root
....................................\.............\.......\...\Repository
....................................\.............\.......\...\Template
....................................\.............\.......\...\Entries.Old
....................................\.............\.......\...\Entries
....................................\.............\.......\...\Entries.Extra.Old
....................................\.............\.......\...\Entries.Extra
....................................\.............\.......\ACC.V
....................................\.............\.......\ALU.V
....................................\.............\.......\CONTROL.V
....................................\.............\.......\IR.V
....................................\.............\.......\MEM.V
....................................\.............\.......\MUX12.V
....................................\.............\.......\MUX16.V
....................................\.............\.......\PC.V
....................................\.............\.......\bus_arbiter.v
....................................\.............\.......\cmd_ack.v
....................................\.............\.......\cmd_decoder.v
....................................\.............\.......\cmd_detector.v
....................................\.............\.......\cmd_generator.v
....................................\.............\.......\cmd_internal_reg.v
....................................\.............\.......\command_if.v
....................................\.............\.......\data_cache_way0.v
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....................................\.............\.......\data_cache_way2.v
....................................\.............\.......\data_cache_way3.v
....................................\.............\.......\data_in_reg.v
....................................\.............\.......\data_port.v
....................................\.............\.......\dma_cntrl.v
....................................\.............\.......\dma_fifo.v
....................................\.............\.......\dma_internal_reg
....................................\.............\...\Repository
....................................\.............\...\Template
....................................\.............\...\Entries.Old
....................................\.............\...\Entries
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....................................\.............\...\Entries.Extra
....................................\.............\SOC_Design.pdf
....................................\.............\Machine_Language\CVS\Root
....................................\.............\................\...\Repository
....................................\.............\................\...\Template
....................................\.............\................\...\Entries.Old
....................................\.............\................\...\Entries
....................................\.............\................\...\Entries.Extra.Old
....................................\.............\................\...\Entries.Extra
....................................\.............\................\program.txt
....................................\.............\Test_Bench_Verilog\CVS\Root
....................................\.............\..................\...\Repository
....................................\.............\..................\...\Template
....................................\.............\..................\...\Entries.Old
....................................\.............\..................\...\Entries
....................................\.............\..................\...\Entries.Extra.Old
....................................\.............\..................\...\Entries.Extra
....................................\.............\..................\Top_level_tb.tf
....................................\.............\Verilog\CVS\Root
....................................\.............\.......\...\Repository
....................................\.............\.......\...\Template
....................................\.............\.......\...\Entries.Old
....................................\.............\.......\...\Entries
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....................................\.............\.......\ACC.V
....................................\.............\.......\ALU.V
....................................\.............\.......\CONTROL.V
....................................\.............\.......\IR.V
....................................\.............\.......\MEM.V
....................................\.............\.......\MUX12.V
....................................\.............\.......\MUX16.V
....................................\.............\.......\PC.V
....................................\.............\.......\bus_arbiter.v
....................................\.............\.......\cmd_ack.v
....................................\.............\.......\cmd_decoder.v
....................................\.............\.......\cmd_detector.v
....................................\.............\.......\cmd_generator.v
....................................\.............\.......\cmd_internal_reg.v
....................................\.............\.......\command_if.v
....................................\.............\.......\data_cache_way0.v
....................................\.............\.......\data_cache_way1.v
....................................\.............\.......\data_cache_way2.v
....................................\.............\.......\data_cache_way3.v
....................................\.............\.......\data_in_reg.v
....................................\.............\.......\data_port.v
....................................\.............\.......\dma_cntrl.v
....................................\.............\.......\dma_fifo.v
....................................\.............\.......\dma_internal_reg