文件名称:verilogChapter-6
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 470kb
- 下载次数：
- 0次
- 提 供 者：
- Alice*****
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续chapter05,给出了从入门到工程应用的一些实例，可以帮助初学者通过学习实例了解和掌握硬件描述语言的基本知识。-Continued chapter05, from entry to the project are given some examples of applications that can help beginners learn instance by hardware descr iption language to understand and master the basics.
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下载文件列表
Chapter-6\spi_controller\bench.vcd
.........\..............\spi_clgen.v
.........\..............\spi_controller.cr.mti
.........\..............\spi_controller.mpf
.........\..............\spi_defines.v
.........\..............\spi_shift.v
.........\..............\spi_slave_model.v
.........\..............\spi_top.v
.........\..............\tb_spi_top.v
.........\..............\timescale.v
.........\..............\transcript
.........\..............\vsim.wlf
.........\..............\wb_master_model.v
.........\..............\chart\Thumbs.db
.........\..............\.....\嗾6-11.bmp
.........\..............\.....\嗾6-12.bmp
.........\..............\.....\嗾6-13.bmp
.........\..............\.....\嗾6-14.bmp
.........\..............\.....\嗾6-17.bmp
.........\..............\.....\嗾6-18.bmp
.........\..............\.....\嗾6-19.bmp
.........\..............\.....\嗾6-7.bmp
.........\..............\chart
.........\..............\wave\Thumbs.db
.........\..............\....\spi_clgen.bmp
.........\..............\....\spi_shift.bmp
.........\..............\....\spi_slave_model.bmp
.........\..............\....\spi_top.bmp
.........\..............\....\tb_spi_top.bmp
.........\..............\....\wb_master_model.bmp
.........\..............\wave
.........\..............\.ork\_info
.........\..............\....\spi_clgen\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\.........\verilog.asm
.........\..............\....\spi_clgen
.........\..............\....\....shift\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\.........\verilog.asm
.........\..............\....\spi_shift
.........\..............\....\.....lave_model\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\...............\verilog.asm
.........\..............\....\spi_slave_model
.........\..............\....\....top\_primary.dat
.........\..............\....\.......\_primary.vhd
.........\..............\....\.......\verilog.asm
.........\..............\....\spi_top
.........\..............\....\tb_spi_top\_primary.dat
.........\..............\....\..........\_primary.vhd
.........\..............\....\..........\verilog.asm
.........\..............\....\tb_spi_top
.........\..............\....\wb_master_model\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\...............\verilog.asm
.........\..............\....\wb_master_model
.........\..............\work
.........\spi_controller
Chapter-6
.........\..............\spi_clgen.v
.........\..............\spi_controller.cr.mti
.........\..............\spi_controller.mpf
.........\..............\spi_defines.v
.........\..............\spi_shift.v
.........\..............\spi_slave_model.v
.........\..............\spi_top.v
.........\..............\tb_spi_top.v
.........\..............\timescale.v
.........\..............\transcript
.........\..............\vsim.wlf
.........\..............\wb_master_model.v
.........\..............\chart\Thumbs.db
.........\..............\.....\嗾6-11.bmp
.........\..............\.....\嗾6-12.bmp
.........\..............\.....\嗾6-13.bmp
.........\..............\.....\嗾6-14.bmp
.........\..............\.....\嗾6-17.bmp
.........\..............\.....\嗾6-18.bmp
.........\..............\.....\嗾6-19.bmp
.........\..............\.....\嗾6-7.bmp
.........\..............\chart
.........\..............\wave\Thumbs.db
.........\..............\....\spi_clgen.bmp
.........\..............\....\spi_shift.bmp
.........\..............\....\spi_slave_model.bmp
.........\..............\....\spi_top.bmp
.........\..............\....\tb_spi_top.bmp
.........\..............\....\wb_master_model.bmp
.........\..............\wave
.........\..............\.ork\_info
.........\..............\....\spi_clgen\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\.........\verilog.asm
.........\..............\....\spi_clgen
.........\..............\....\....shift\_primary.dat
.........\..............\....\.........\_primary.vhd
.........\..............\....\.........\verilog.asm
.........\..............\....\spi_shift
.........\..............\....\.....lave_model\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\...............\verilog.asm
.........\..............\....\spi_slave_model
.........\..............\....\....top\_primary.dat
.........\..............\....\.......\_primary.vhd
.........\..............\....\.......\verilog.asm
.........\..............\....\spi_top
.........\..............\....\tb_spi_top\_primary.dat
.........\..............\....\..........\_primary.vhd
.........\..............\....\..........\verilog.asm
.........\..............\....\tb_spi_top
.........\..............\....\wb_master_model\_primary.dat
.........\..............\....\...............\_primary.vhd
.........\..............\....\...............\verilog.asm
.........\..............\....\wb_master_model
.........\..............\work
.........\spi_controller
Chapter-6