文件名称:verilogChapter-5
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 387kb
- 下载次数：
- 0次
- 提 供 者：
- Alice*****
- 相关连接：
- 无
- 下载说明：
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续chapter04,给出了从入门到工程应用的一些实例，可以帮助初学者通过学习实例了解和掌握硬件描述语言的基本知识。-Continued chapter04, from entry to the project are given some examples of applications that can help beginners learn instance by hardware descr iption language to understand and master the basics.
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下载文件列表
Chapter-5\5.2\mult16.cr.mti
.........\...\mult16.mpf
.........\...\multiplication.v
.........\...\multiplication_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾5-5.bmp
.........\...\.....\嗾5-6.bmp
.........\...\.....\表5-1.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\multiplication.bmp
.........\...\....\multiplication_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\multiplication\_primary.dat
.........\...\....\..............\_primary.vhd
.........\...\....\..............\verilog.asm
.........\...\....\multiplication
.........\...\....\.............._testbench\_primary.dat
.........\...\....\........................\_primary.vhd
.........\...\....\........................\verilog.asm
.........\...\....\multiplication_testbench
.........\...\work
.........\5.2
.........\..3\traffic.cr.mti
.........\...\traffic.mpf
.........\...\traffic.v
.........\...\traffic_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾5-7.bmp
.........\...\.....\嗾5-9.bmp
.........\...\.....\表5-3.bmp
.........\...\.....\表5-3（緭）.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\traffic.bmp
.........\...\....\traffic_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\traffic\_primary.dat
.........\...\....\.......\_primary.vhd
.........\...\....\.......\verilog.asm
.........\...\....\traffic
.........\...\....\......._testbench\_primary.dat
.........\...\....\.................\_primary.vhd
.........\...\....\.................\verilog.asm
.........\...\....\traffic_testbench
.........\...\work
.........\5.3
.........\..4\note.txt
.........\...\pci.cr.mti
.........\...\pci.mpf
.........\...\pci_tb.v
.........\...\state_machine.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾5-14.bmp
.........\...\.....\嗾5-15.bmp
.........\...\.....\表5-4(緭1-1).bmp
.........\...\.....\表5-4(緭1-2).bmp
.........\...\.....\表5-4(緭2).bmp
.........\...\.....\表5-4.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\pci_tb.bmp
.........\...\....\state_machine.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\base_addr_chk\_primary.dat
.........\...\....\.............\_primary.vhd
.........\...\....\.............\verilog.asm
.........\...\....\base_addr_chk
.........\...\....\.kend_daemon\_primary.dat
.........\...\....\............\_primary.vhd
.........\...\....\............\verilog.asm
.........\...\....\bkend_daemon
.........\...\....\config_mux\_primary.dat
.........\...\....\..........\_primary.vhd
.........\...\....\..........\verilog.asm
.........\...\....\config_mux
.........\...\....\glue\_primary.dat
.........\...\....\....\_primary.vhd
.........\...\....\....\verilog.asm
.........\...\....\glue
.........\...\....\pargen\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\pargen
.........\...\....\.ci_clk_reset\_primary.dat
.........\...\....\.............\_primary.vhd
.........\...\....\.............\verilog.asm
.........\...\....\pci_clk_reset
.........\...\....\....stim\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm
.........\...\mult16.mpf
.........\...\multiplication.v
.........\...\multiplication_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾5-5.bmp
.........\...\.....\嗾5-6.bmp
.........\...\.....\表5-1.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\multiplication.bmp
.........\...\....\multiplication_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\multiplication\_primary.dat
.........\...\....\..............\_primary.vhd
.........\...\....\..............\verilog.asm
.........\...\....\multiplication
.........\...\....\.............._testbench\_primary.dat
.........\...\....\........................\_primary.vhd
.........\...\....\........................\verilog.asm
.........\...\....\multiplication_testbench
.........\...\work
.........\5.2
.........\..3\traffic.cr.mti
.........\...\traffic.mpf
.........\...\traffic.v
.........\...\traffic_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾5-7.bmp
.........\...\.....\嗾5-9.bmp
.........\...\.....\表5-3.bmp
.........\...\.....\表5-3（緭）.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\traffic.bmp
.........\...\....\traffic_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\traffic\_primary.dat
.........\...\....\.......\_primary.vhd
.........\...\....\.......\verilog.asm
.........\...\....\traffic
.........\...\....\......._testbench\_primary.dat
.........\...\....\.................\_primary.vhd
.........\...\....\.................\verilog.asm
.........\...\....\traffic_testbench
.........\...\work
.........\5.3
.........\..4\note.txt
.........\...\pci.cr.mti
.........\...\pci.mpf
.........\...\pci_tb.v
.........\...\state_machine.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾5-14.bmp
.........\...\.....\嗾5-15.bmp
.........\...\.....\表5-4(緭1-1).bmp
.........\...\.....\表5-4(緭1-2).bmp
.........\...\.....\表5-4(緭2).bmp
.........\...\.....\表5-4.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\pci_tb.bmp
.........\...\....\state_machine.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\base_addr_chk\_primary.dat
.........\...\....\.............\_primary.vhd
.........\...\....\.............\verilog.asm
.........\...\....\base_addr_chk
.........\...\....\.kend_daemon\_primary.dat
.........\...\....\............\_primary.vhd
.........\...\....\............\verilog.asm
.........\...\....\bkend_daemon
.........\...\....\config_mux\_primary.dat
.........\...\....\..........\_primary.vhd
.........\...\....\..........\verilog.asm
.........\...\....\config_mux
.........\...\....\glue\_primary.dat
.........\...\....\....\_primary.vhd
.........\...\....\....\verilog.asm
.........\...\....\glue
.........\...\....\pargen\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\pargen
.........\...\....\.ci_clk_reset\_primary.dat
.........\...\....\.............\_primary.vhd
.........\...\....\.............\verilog.asm
.........\...\....\pci_clk_reset
.........\...\....\....stim\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm