文件名称:verilogChapter-4
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 333kb
- 下载次数：
- 0次
- 提 供 者：
- Alice*****
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
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介绍说明－－下载内容均来自于网络，请自行研究使用
续chapter03,给出了从入门到工程应用的一些实例，可以帮助初学者通过学习实例了解和掌握硬件描述语言的基本知识。-Continued chapter03, from entry to the project are given some examples of applications that can help beginners learn instance by hardware descr iption language to understand and master the basics.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Chapter-4\4.1\bin_enc.cr.mti
.........\...\bin_enc.mpf
.........\...\bin_enc.v
.........\...\bin_enc_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾4-2.bmp
.........\...\.....\表4-1.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\bin_enc.bmp
.........\...\....\bin_enc_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\bin_enc\_primary.dat
.........\...\....\.......\_primary.vhd
.........\...\....\.......\verilog.asm
.........\...\....\bin_enc
.........\...\....\......._testbench\_primary.dat
.........\...\....\.................\_primary.vhd
.........\...\....\.................\verilog.asm
.........\...\....\bin_enc_testbench
.........\...\work
.........\4.1
.........\..2\manch_de.rpt
.........\...\manch_de.v
.........\...\manch_de_testbench.v
.........\...\manch_en.rpt
.........\...\manch_en.v
.........\...\manch_en_de.cr.mti
.........\...\manch_en_de.mpf
.........\...\manch_en_de.v
.........\...\manch_en_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾4-5.bmp
.........\...\.....\嗾4-7.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\manch_de.bmp
.........\...\....\manch_de_testbench.bmp
.........\...\....\manch_en.bmp
.........\...\....\manch_en_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\manch_de\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm
.........\...\....\manch_de
.........\...\....\........_testbench\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\..................\verilog.asm
.........\...\....\manch_de_testbench
.........\...\....\......en\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm
.........\...\....\manch_en
.........\...\....\........_de\_primary.dat
.........\...\....\...........\_primary.vhd
.........\...\....\...........\verilog.asm
.........\...\....\manch_en_de
.........\...\....\.........testbench\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\..................\verilog.asm
.........\...\....\manch_en_testbench
.........\...\work
.........\4.2
.........\..3\Signal_detect.v
.........\...\decode.v
.........\...\decode_ter.rpt
.........\...\decode_testbench.v
.........\...\miller_de.cr.mti
.........\...\miller_de.mpf
.........\...\miller_de.v
.........\...\miller_de_testbench.v
.........\...\signal_detect_testbench.v
.........\...\signal_ter.rpt
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾4-11.bmp
.........\...\.....\嗾4-13.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\decode.bmp
.........\...\....\decode_testbench.bmp
.........\...\....\miller_de.bmp
.........\...\....\miller_de_testbench.bmp
.........\...\....\signal_detect.bmp
.........\...\....\signal_detect_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\decode\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\decode
.........\...\....\......_testbench\_primary.dat
.........\...\....\................\_primary.vhd
.........\...\bin_enc.mpf
.........\...\bin_enc.v
.........\...\bin_enc_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾4-2.bmp
.........\...\.....\表4-1.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\bin_enc.bmp
.........\...\....\bin_enc_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\bin_enc\_primary.dat
.........\...\....\.......\_primary.vhd
.........\...\....\.......\verilog.asm
.........\...\....\bin_enc
.........\...\....\......._testbench\_primary.dat
.........\...\....\.................\_primary.vhd
.........\...\....\.................\verilog.asm
.........\...\....\bin_enc_testbench
.........\...\work
.........\4.1
.........\..2\manch_de.rpt
.........\...\manch_de.v
.........\...\manch_de_testbench.v
.........\...\manch_en.rpt
.........\...\manch_en.v
.........\...\manch_en_de.cr.mti
.........\...\manch_en_de.mpf
.........\...\manch_en_de.v
.........\...\manch_en_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾4-5.bmp
.........\...\.....\嗾4-7.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\manch_de.bmp
.........\...\....\manch_de_testbench.bmp
.........\...\....\manch_en.bmp
.........\...\....\manch_en_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\manch_de\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm
.........\...\....\manch_de
.........\...\....\........_testbench\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\..................\verilog.asm
.........\...\....\manch_de_testbench
.........\...\....\......en\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm
.........\...\....\manch_en
.........\...\....\........_de\_primary.dat
.........\...\....\...........\_primary.vhd
.........\...\....\...........\verilog.asm
.........\...\....\manch_en_de
.........\...\....\.........testbench\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\..................\verilog.asm
.........\...\....\manch_en_testbench
.........\...\work
.........\4.2
.........\..3\Signal_detect.v
.........\...\decode.v
.........\...\decode_ter.rpt
.........\...\decode_testbench.v
.........\...\miller_de.cr.mti
.........\...\miller_de.mpf
.........\...\miller_de.v
.........\...\miller_de_testbench.v
.........\...\signal_detect_testbench.v
.........\...\signal_ter.rpt
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾4-11.bmp
.........\...\.....\嗾4-13.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\decode.bmp
.........\...\....\decode_testbench.bmp
.........\...\....\miller_de.bmp
.........\...\....\miller_de_testbench.bmp
.........\...\....\signal_detect.bmp
.........\...\....\signal_detect_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\decode\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\decode
.........\...\....\......_testbench\_primary.dat
.........\...\....\................\_primary.vhd