文件名称:verilogChapter-2
- 所属分类：
- VHDL编程
- 资源属性：
- [ASM] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 222kb
- 下载次数：
- 0次
- 提 供 者：
- Alice*****
- 相关连接：
- 无
- 下载说明：
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续chapter01,给出了从入门到工程应用的一些实例，可以帮助初学者通过学习实例了解和掌握硬件描述语言的基本知识。-Continue chapter01, from entry to the project are given some examples of applications that can help beginners learn instance by hardware descr iption language to understand and master the basics.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Chapter-2\2.1\adder
.........\...\adder.cr.mti
.........\...\adder.mpf
.........\...\adder.v
.........\...\adder_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-2.bmp
.........\...\.....\表2-1.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\adder.bmp
.........\...\....\adder_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\adder\_primary.dat
.........\...\....\.....\_primary.vhd
.........\...\....\.....\verilog.asm
.........\...\....\adder
.........\...\....\....._testbench\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\...............\verilog.asm
.........\...\....\adder_testbench
.........\...\work
.........\2.1
.........\..2\full_add.cr.mti
.........\...\full_add.mpf
.........\...\full_add.v
.........\...\full_add_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-4.bmp
.........\...\.....\表2-2.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\full_add.bmp
.........\...\....\full_add_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\full_add\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm
.........\...\....\full_add
.........\...\....\........_testbench\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\..................\verilog.asm
.........\...\....\full_add_testbench
.........\...\work
.........\2.2
.........\..3\adder4.cr.mti
.........\...\adder4.mpf
.........\...\adder4.v
.........\...\adder4_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-7.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\adder4.bmp
.........\...\....\adder4_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\adder4\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\adder4
.........\...\....\......_testbench\_primary.dat
.........\...\....\................\_primary.vhd
.........\...\....\................\verilog.asm
.........\...\....\adder4_testbench
.........\...\work
.........\2.3
.........\..4\coun4_testbench.v
.........\...\count4.cr.mti
.........\...\count4.mpf
.........\...\count4.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-10.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\coun4.bmp
.........\...\....\coun4_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\coun4_testbench\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\...............\verilog.asm
.........\...\....\coun4_testbench
.........\...\....\....t4\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\count4
.........\...\work
.........\2.4
.........\..5\count60.cr.mti
.........\...\adder.cr.mti
.........\...\adder.mpf
.........\...\adder.v
.........\...\adder_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-2.bmp
.........\...\.....\表2-1.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\adder.bmp
.........\...\....\adder_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\adder\_primary.dat
.........\...\....\.....\_primary.vhd
.........\...\....\.....\verilog.asm
.........\...\....\adder
.........\...\....\....._testbench\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\...............\verilog.asm
.........\...\....\adder_testbench
.........\...\work
.........\2.1
.........\..2\full_add.cr.mti
.........\...\full_add.mpf
.........\...\full_add.v
.........\...\full_add_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-4.bmp
.........\...\.....\表2-2.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\full_add.bmp
.........\...\....\full_add_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\full_add\_primary.dat
.........\...\....\........\_primary.vhd
.........\...\....\........\verilog.asm
.........\...\....\full_add
.........\...\....\........_testbench\_primary.dat
.........\...\....\..................\_primary.vhd
.........\...\....\..................\verilog.asm
.........\...\....\full_add_testbench
.........\...\work
.........\2.2
.........\..3\adder4.cr.mti
.........\...\adder4.mpf
.........\...\adder4.v
.........\...\adder4_testbench.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-7.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\adder4.bmp
.........\...\....\adder4_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\adder4\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\adder4
.........\...\....\......_testbench\_primary.dat
.........\...\....\................\_primary.vhd
.........\...\....\................\verilog.asm
.........\...\....\adder4_testbench
.........\...\work
.........\2.3
.........\..4\coun4_testbench.v
.........\...\count4.cr.mti
.........\...\count4.mpf
.........\...\count4.v
.........\...\transcript
.........\...\vsim.wlf
.........\...\chart\Thumbs.db
.........\...\.....\嗾2-10.bmp
.........\...\chart
.........\...\wave\Thumbs.db
.........\...\....\coun4.bmp
.........\...\....\coun4_testbench.bmp
.........\...\wave
.........\...\.ork\_info
.........\...\....\coun4_testbench\_primary.dat
.........\...\....\...............\_primary.vhd
.........\...\....\...............\verilog.asm
.........\...\....\coun4_testbench
.........\...\....\....t4\_primary.dat
.........\...\....\......\_primary.vhd
.........\...\....\......\verilog.asm
.........\...\....\count4
.........\...\work
.........\2.4
.........\..5\count60.cr.mti