文件名称:verilogChapter-1
- 所属分类:
- VHDL编程
- 资源属性:
- [ASM] [源码]
- 上传时间:
- 2012-11-26
- 文件大小:
- 155kb
- 下载次数:
- 0次
- 提 供 者:
- Alice*****
- 相关连接:
- 无
- 下载说明:
- 别用迅雷下载,失败请重下,重下不扣分!
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介绍说明--下载内容均来自于网络,请自行研究使用
给出了从入门到工程应用的一些实例,可以帮助初学者通过学习实例了解和掌握硬件描述语言的基本知识。-From entry to the project gives some examples of applications that can help beginners learn instance by hardware descr iption language to understand and master the basics.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Chapter-1\adder\adder.cr.mti
.........\.....\adder.mpf
.........\.....\adder.v
.........\.....\adder_testbench.do
.........\.....\adder_testbench.v
.........\.....\transcript
.........\.....\vsim.wlf
.........\.....\chart\Thumbs.db
.........\.....\.....\嗾1-3.bmp
.........\.....\.....\嗾1-4.bmp
.........\.....\.....\嗾1-5.bmp
.........\.....\.....\嗾1-6.bmp
.........\.....\.....\嗾1-7.bmp
.........\.....\.....\嗾1-8.bmp
.........\.....\chart
.........\.....\work\_info
.........\.....\....\adder\_primary.dat
.........\.....\....\.....\_primary.vhd
.........\.....\....\.....\transcript
.........\.....\....\.....\verilog.txt.asm
.........\.....\....\adder
.........\.....\....\....._testbench\_primary.dat
.........\.....\....\...............\_primary.vhd
.........\.....\....\...............\verilog.asm
.........\.....\....\adder_testbench
.........\.....\work
.........\adder
Chapter-1
.........\.....\adder.mpf
.........\.....\adder.v
.........\.....\adder_testbench.do
.........\.....\adder_testbench.v
.........\.....\transcript
.........\.....\vsim.wlf
.........\.....\chart\Thumbs.db
.........\.....\.....\嗾1-3.bmp
.........\.....\.....\嗾1-4.bmp
.........\.....\.....\嗾1-5.bmp
.........\.....\.....\嗾1-6.bmp
.........\.....\.....\嗾1-7.bmp
.........\.....\.....\嗾1-8.bmp
.........\.....\chart
.........\.....\work\_info
.........\.....\....\adder\_primary.dat
.........\.....\....\.....\_primary.vhd
.........\.....\....\.....\transcript
.........\.....\....\.....\verilog.txt.asm
.........\.....\....\adder
.........\.....\....\....._testbench\_primary.dat
.........\.....\....\...............\_primary.vhd
.........\.....\....\...............\verilog.asm
.........\.....\....\adder_testbench
.........\.....\work
.........\adder
Chapter-1