文件名称:ClockDiv
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本程序以XILINX公司的ISE８.２为开发平台，采用VHDL为开发语言，实现了对一个时钟信号分频的功能-the procedures to XILINX ISE8.2 for the development platform VHDL used for the development of language, the right to achieve a clock frequency of the signal function
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下载文件列表
压缩包 : 115157696clockdiv.rar 列表 ClockDiv.cmd_log ClockDiv.ise_ISE_Backup ClockDiv.lso ClockDiv.ngc ClockDiv.ngd ClockDiv.ngr ClockDiv.ntrc_log ClockDiv.pad ClockDiv.par ClockDiv.pcf ClockDiv.stx ClockDiv.syr ClockDiv.tdo clockdiv.twr clockdiv.twx ClockDiv.udo ClockDiv.unroutes ClockDiv.xpi ClockDiv.xst ClockDiv_last_par.ncd ClockDiv_map.ncd ClockDiv_map.mrp ClockDiv_map.ngm ClockDiv_pad.csv ClockDiv_pad.txt ClockDiv_summary.html ClockDiv_tbw.ano ClockDiv_tbw.ant ClockDiv_tbw.jhd ClockDiv_tbw.mdo ClockDiv_tbw.ndo ClockDiv_tbw.tbw ClockDiv_tbw.tdo ClockDiv_tbw.udo ClockDiv_tbw.vhw ClockDiv_tbw.xwv ClockDiv_tbw.xwv_bak ClockDiv_tbw_beh.prj ClockDiv_tbw_bencher.prj ClockDiv_tbw_gen.prj ClockDiv_tbw_isim_beh.exe ClockDiv_tbw_isim_par.exe ClockDiv_tbw_par.prj ClockDiv_tbw_tbxr.exe genExpectedResults.cmd isim.cmd isim.log isim.hdlsourcefiles isimwavedata.xwv pepExtractor.prj results.txt transcript xilinxsim.ini _ngo\netlist.lst _xmsgs\fuse.xmsgs _xmsgs\map.xmsgs _xmsgs\netgen.xmsgs _xmsgs\ngdbuild.xmsgs _xmsgs\par.xmsgs _xmsgs\trce.xmsgs _xmsgs\vhpcomp.xmsgs _xmsgs\xst.xmsgs isim\simprim_ver.auxlib\ffsrce\ffsrce.h isim\simprim_ver.auxlib\ffsrce\mingw\ffsrce.obj isim\simprim_ver.auxlib\hdllib.ref isim\simprim_ver.auxlib\sffsrce\mingw\sffsrce.obj isim\simprim_ver.auxlib\sffsrce\sffsrce.h isim\simprim_ver.auxlib\_x___b_u_f\mingw\_x___b_u_f.obj isim\simprim_ver.auxlib\_x___b_u_f\_x___b_u_f.h isim\simprim_ver.auxlib\_x___c_k_b_u_f\mingw\_x___c_k_b_u_f.obj isim\simprim_ver.auxlib\_x___c_k_b_u_f\_x___c_k_b_u_f.h isim\simprim_ver.auxlib\_x___f_f\mingw\_x___f_f.obj isim\simprim_ver.auxlib\_x___f_f\_x___f_f.h isim\simprim_ver.auxlib\_x___i_n_v\mingw\_x___i_n_v.obj isim\simprim_ver.auxlib\_x___i_n_v\_x___i_n_v.h isim\simprim_ver.auxlib\_x___i_p_a_d\mingw\_x___i_p_a_d.obj isim\simprim_ver.auxlib\_x___i_p_a_d\_x___i_p_a_d.h isim\simprim_ver.auxlib\_x___l_u_t4\mingw\_x___l_u_t4.obj isim\simprim_ver.auxlib\_x___l_u_t4\_x___l_u_t4.h isim\simprim_ver.auxlib\_x___o_b_u_f\mingw\_x___o_b_u_f.obj isim\simprim_ver.auxlib\_x___o_b_u_f\_x___o_b_u_f.h isim\simprim_ver.auxlib\_x___o_n_e\mingw\_x___o_n_e.obj isim\simprim_ver.auxlib\_x___o_n_e\_x___o_n_e.h isim\simprim_ver.auxlib\_x___o_p_a_d\mingw\_x___o_p_a_d.obj isim\simprim_ver.auxlib\_x___o_p_a_d\_x___o_p_a_d.h isim\simprim_ver.auxlib\_x___s_f_f\mingw\_x___s_f_f.obj isim\simprim_ver.auxlib\_x___s_f_f\_x___s_f_f.h isim\simprim_ver.auxlib\_x___z_e_r_o\mingw\_x___z_e_r_o.obj isim\simprim_ver.auxlib\_x___z_e_r_o\_x___z_e_r_o.h isim\work\clockdiv\behavioral.h isim\work\clockdiv\mingw\behavioral.obj isim\work\clockdiv_tbw\mingw\testbench_arch.obj isim\work\clockdiv_tbw\testbench_arch.h isim\work\clockdiv_tbw\xsimtestbench_arch.cpp isim\work\glbl\glbl.h isim\work\glbl\mingw\glbl.obj isim\work\hdllib.ref isim\work\hdpdeps.ref isim\work\sub00\vhpl00.vho isim\work\sub00\vhpl01.vho isim\work\sub00\vhpl02.vho isim\work\sub00\vhpl03.vho isim\work\vlg27\_clock_div.bin isim\work\vlg2D\glbl.bin isim\work\_clock_div\mingw\_clock_div.obj isim\work\_clock_div\_clock_div.h isim.tmp_save\_1 netgen\map\ClockDiv_map.nlf netgen\map\ClockDiv_map.sdf netgen\map\ClockDiv_map.vhd netgen\par\ClockDiv_timesim.nlf netgen\par\clockdiv_timesim.sdf netgen\par\ClockDiv_timesim.vhd netgen\synthesis\ClockDiv_synthesis.nlf netgen\synthesis\ClockDiv_synthesis.v netgen\translate\ClockDiv_translate.nlf netgen\translate\ClockDiv_translate.vhd work\_info xst\work\hdllib.ref xst\work\hdpdeps.ref xst\work\sub00\vhpl00.vho xst\work\sub00\vhpl01.vho __ISE_repository_ClockDiv.ise_.lock ClockDiv.ise ClockDiv.ncd ClockDiv.prj ClockDiv.vhd ClockDiv.bld xst\dump.xst\ClockDiv.prj\ngx\notopt xst\dump.xst\ClockDiv.prj\ngx\opt isim\simprim_ver.auxlib\ffsrce\mingw isim\simprim_ver.auxlib\sffsrce\mingw isim\simprim_ver.auxlib\_x___b_u_f\mingw isim\simprim_ver.auxlib\_x___c_k_b_u_f\mingw isim\simprim_ver.auxlib\_x___f_f\mingw isim\simprim_ver.auxlib\_x___i_n_v\mingw isim\simprim_ver.auxlib\_x___i_p_a_d\mingw isim\simprim_ver.auxlib\_x___l_u_t4\mingw isim\simprim_ver.auxlib\_x___o_b_u_f\mingw isim\simprim_ver.auxlib\_x___o_n_e\mingw isim\simprim_ver.auxlib\_x___o_p_a_d\mingw isim\simprim_ver.auxlib\_x___s_f_f\mingw isim\simprim_ver.auxlib\_x___z_e_r_o\mingw isim\work\clockdiv\mingw isim\work\clockdiv_tbw\mingw isim\work\glbl\mingw isim\work\_clock_div\mingw xst\dump.xst\ClockDiv.prj\ngx isim\simprim_ver.auxlib\ffsrce isim\simprim_ver.auxlib\sffsrce isim\simprim_ver.auxlib\_x___b_u_f isim\simprim_ver.auxlib\_x___c_k_b_u_f isim\simprim_ver.auxlib\_x___f_f isim\simprim_ver.auxlib\_x___i_n_v isim\simprim_ver.auxlib\_x___i_p_a_d isim\simprim_ver.auxlib\_x___l_u_t4 isim\simprim_ver.auxlib\_x___o_b_u_f isim\simprim_ver.auxlib\_x___o_n_e isim\simprim_ver.auxlib\_x___o_p_a_d isim\simprim_ver.auxlib\_x___s_f_f isim\simprim_ver.auxlib\_x___z_e_r_o isim\work\clockdiv isim\work\clockdiv_tbw isim\work\glbl isim\work\sub00 isim\work\vlg27 isim\work\vlg2D isim\work\_clock_div xst\dump.xst\ClockDiv.prj xst\work\sub00 isim\simprim_ver.auxlib isim\work netgen\map netgen\par netgen\synthesis netgen\translate work\_temp xst\dump.xst xst\projnav.tmp xst\work _ngo _xmsgs isim isim.tmp_save netgen work xst