资源列表

« 1 2 ... .79 .80 .81 .82 .83 584.85 .86 .87 .88 .89 ... 8590 »

[软件工程UniEAP_V4_3_FAQ

说明:UniEAP V4.3 部署与配置FAQ,学习UniEAP前必看
<TONY> 在 2025-02-06 上传 | 大小:349kb | 下载:0

[软件工程SPFlashTool-SecBoot

说明:spflashtools o TAKE backup OF STOCK ROM
<lejini> 在 2025-02-06 上传 | 大小:7.57mb | 下载:0

[软件工程ROOT

说明:rooting any android phone
<lejini> 在 2025-02-06 上传 | 大小:2.48mb | 下载:0

[软件工程input-capture-program

说明:飞思卡尔xs128的输入捕捉程序,为.doc格式的-Freescale xs128 input capture program for .doc format
<ssq> 在 2025-02-06 上传 | 大小:5kb | 下载:0

[软件工程E532

说明:Manual u-controler PIC for all students who want to learn
<AnghelLiviu> 在 2025-02-06 上传 | 大小:4.21mb | 下载:0

[软件工程Hall-C-The-Little-Haskeller

说明:Hall C The Little Haskeller 1991
<Freak> 在 2025-02-06 上传 | 大小:176kb | 下载:0

[软件工程project1.cr

说明:Take the whole expression into a primed parenthesis to obtain F. Hence, the function becomes suitable for the NAND implementation.
<john> 在 2025-02-06 上传 | 大小:180kb | 下载:0

[软件工程TOFED_Dataflow

说明:Take its complement by applying DeMorgan’s theorem to obtain F in the form of product of complemented products.
<john> 在 2025-02-06 上传 | 大小:154kb | 下载:0

[软件工程TOFED_Stru

说明:Check all bubbles in the logic diagram. For every bubble that is not compensated by another bubble along the same line, insert an inverter (a one-input NAND gate) or complement the input literal.
<john> 在 2025-02-06 上传 | 大小:1kb | 下载:0

[软件工程TOFED_TB_1

说明:A 4 bit twisted ring counter is a sequential circuit which produces the following sequence of output values: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001 and then repeats. Design a circuit for a 4 bit twiste
<john> 在 2025-02-06 上传 | 大小:2kb | 下载:0

[软件工程projectaq1.cr

说明:Write VHDL specifications for an eight bit twisted ring counter based on each of the designs in the previous problem. Look at the synthesis report generated by the design tools (use the Spartan 2 xc2s15-cs144-
<john> 在 2025-02-06 上传 | 大小:44kb | 下载:0

[软件工程project

说明:The code for the second version is shown below. The synthesis report indicates that this uses 4 flip flops and 11 LUTs of various types. The maximum estimated clock frequency is 200 MHz. These results are cons
<john> 在 2025-02-06 上传 | 大小:379kb | 下载:0
« 1 2 ... .79 .80 .81 .82 .83 584.85 .86 .87 .88 .89 ... 8590 »

源码中国 www.ymcn.org