文件名称:Asynchronous-FIFO-design
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异步FIFO是一种先进先出的电路，在异步电路中，由于时钟之间周期和相位完全独立，因而数据丢失概率不为零。如何设计一个高可靠性、高速异步的FIFO是一个难点，本代码介绍了一种解决方法。-Asynchronous FIFO is a kind of advanced first out circuit, in asynchronous circuit, as the clock cycle and phase between full independence, thus data loss probability is not zero. How to design a high reliability, high speed asynchronous FIFO is a difficulty, this code introduced a kind of solution.
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下载文件列表
异步FIFO设计\async_cmp.v
............\async_fifo.v
............\dp_ram.v
............\rptr_empty.v
............\wptr_full.v
异步FIFO设计
............\async_fifo.v
............\dp_ram.v
............\rptr_empty.v
............\wptr_full.v
异步FIFO设计