文件名称:clock1
- 所属分类：
- VHDL编程
- 资源属性：
- 上传时间：
- 2012-11-26
- 文件大小：
- 425kb
- 下载次数：
- 0次
- 提 供 者：
- zhangs*******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
下载
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失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
本程序用VHDL编写数字钟，具有定点报时，手动调整时间等功能，能下载到板子上显示时间。-This program written by VHDL digital clock, with a fixed broadcast, manually adjust the time and other functions, can be downloaded to display the time on the board.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clock1\chang.vhd
......\clock.asm.rpt
......\clock.cdf
......\clock.done
......\clock.dpf
......\clock.fit.rpt
......\clock.fit.smsg
......\clock.fit.summary
......\clock.flow.rpt
......\clock.map.rpt
......\clock.map.summary
......\clock.pin
......\clock.pof
......\clock.qpf
......\clock.qsf
......\clock.qws
......\clock.sim.rpt
......\clock.tan.rpt
......\clock.tan.summary
......\clock.vhd
......\clock.vhd.bak
......\clock.vwf
......\clock_assignment_defaults.qdf
......\db\clock.asm.qmsg
......\..\clock.cbx.xml
......\..\clock.cmp.cdb
......\..\clock.cmp.hdb
......\..\clock.cmp.logdb
......\..\clock.cmp.rdb
......\..\clock.cmp.tdb
......\..\clock.cmp0.ddb
......\..\clock.db_info
......\..\clock.eco.cdb
......\..\clock.fit.qmsg
......\..\clock.hier_info
......\..\clock.hif
......\..\clock.map.cdb
......\..\clock.map.hdb
......\..\clock.map.logdb
......\..\clock.map.qmsg
......\..\clock.pre_map.cdb
......\..\clock.pre_map.hdb
......\..\clock.rtlv.hdb
......\..\clock.rtlv_sg.cdb
......\..\clock.rtlv_sg_swap.cdb
......\..\clock.sgdiff.cdb
......\..\clock.sgdiff.hdb
......\..\clock.signalprobe.cdb
......\..\clock.sim.cvwf
......\..\clock.sld_design_entry.sci
......\..\clock.sld_design_entry_dsc.sci
......\..\clock.syn_hier_info
......\..\clock.tan.qmsg
......\..\clock.tis_db_list.ddb
......\..\prev_cmp_clock.asm.qmsg
......\..\prev_cmp_clock.fit.qmsg
......\..\prev_cmp_clock.map.qmsg
......\..\prev_cmp_clock.qmsg
......\..\prev_cmp_clock.sim.qmsg
......\..\prev_cmp_clock.tan.qmsg
......\..\wed.wsf
......\div.vhd
......\div.vhd.bak
......\hour.vhd
......\hour.vhd.bak
......\minute.vhd
......\minute.vhd.bak
......\rel.vhd
......\second.vhd
......\second.vhd.bak
......\seltime.vhd
......\show.vhd
......\db
clock1
......\clock.asm.rpt
......\clock.cdf
......\clock.done
......\clock.dpf
......\clock.fit.rpt
......\clock.fit.smsg
......\clock.fit.summary
......\clock.flow.rpt
......\clock.map.rpt
......\clock.map.summary
......\clock.pin
......\clock.pof
......\clock.qpf
......\clock.qsf
......\clock.qws
......\clock.sim.rpt
......\clock.tan.rpt
......\clock.tan.summary
......\clock.vhd
......\clock.vhd.bak
......\clock.vwf
......\clock_assignment_defaults.qdf
......\db\clock.asm.qmsg
......\..\clock.cbx.xml
......\..\clock.cmp.cdb
......\..\clock.cmp.hdb
......\..\clock.cmp.logdb
......\..\clock.cmp.rdb
......\..\clock.cmp.tdb
......\..\clock.cmp0.ddb
......\..\clock.db_info
......\..\clock.eco.cdb
......\..\clock.fit.qmsg
......\..\clock.hier_info
......\..\clock.hif
......\..\clock.map.cdb
......\..\clock.map.hdb
......\..\clock.map.logdb
......\..\clock.map.qmsg
......\..\clock.pre_map.cdb
......\..\clock.pre_map.hdb
......\..\clock.rtlv.hdb
......\..\clock.rtlv_sg.cdb
......\..\clock.rtlv_sg_swap.cdb
......\..\clock.sgdiff.cdb
......\..\clock.sgdiff.hdb
......\..\clock.signalprobe.cdb
......\..\clock.sim.cvwf
......\..\clock.sld_design_entry.sci
......\..\clock.sld_design_entry_dsc.sci
......\..\clock.syn_hier_info
......\..\clock.tan.qmsg
......\..\clock.tis_db_list.ddb
......\..\prev_cmp_clock.asm.qmsg
......\..\prev_cmp_clock.fit.qmsg
......\..\prev_cmp_clock.map.qmsg
......\..\prev_cmp_clock.qmsg
......\..\prev_cmp_clock.sim.qmsg
......\..\prev_cmp_clock.tan.qmsg
......\..\wed.wsf
......\div.vhd
......\div.vhd.bak
......\hour.vhd
......\hour.vhd.bak
......\minute.vhd
......\minute.vhd.bak
......\rel.vhd
......\second.vhd
......\second.vhd.bak
......\seltime.vhd
......\show.vhd
......\db
clock1