文件名称:design0
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
verilog coding for basic gates
(系统自动生成,下载前可以参看下载内容)
下载文件列表
design0\0.mgf
.......\1.mgf
.......\3.mgf
.......\bde.set
.......\compile\contents.lib~
.......\.......\design0.epr
.......\.......\design0.erf
.......\.......\design0.opt
.......\.......\mega.bin
.......\.......\mega.dbg
.......\.......\mega.elb
.......\.......\mega.itf
.......\.......\mega.mod
.......\.......\mega.off
.......\.......\sources.sth
.......\.......\vcp.mod
.......\.......\vcp.top
.......\.......\wave1.dat
.......\compile.cfg
.......\design0.adf
.......\design0.LIB
.......\design0.wsp
.......\elaboration.log
.......\log\console.log
.......\projlib.cfg
.......\src\2realization\func1.awf
.......\...\............\func1.v
.......\...\............\func2.awf
.......\...\............\func2.v
.......\...\............\func3.awf
.......\...\............\func3.v
.......\...\............\func4.awf
.......\...\............\func4.v
.......\...\Arithmetic units\full adder using half adder.awf
.......\...\................\full adder using half adder.v
.......\...\................\full adder.awf
.......\...\................\full adder.v
.......\...\................\full sub using half sub.awf
.......\...\................\full sub using half sub.v
.......\...\................\full sub.awf
.......\...\................\full sub.v
.......\...\................\haf adder.awf
.......\...\................\half adder.v
.......\...\................\half sub.awf
.......\...\................\half sub.v
.......\...\arithmetic units 2\4 bit bcd adder.v
.......\...\..................\4 bit parallel adder using full adder.v
.......\...\..................\4 bit parallel adder.awf
.......\...\..................\4 bit parallel sub.awf
.......\...\..................\4 bit parallel sub.v
.......\...\..................\8 bit ps using 4 bit ps.v
.......\...\..................\8 bit pa using 4bit pa.awf
.......\...\..................\8 bit parallel adder using 4 bit pa.v
.......\...\..................\8 bit parallel adder.awf
.......\...\..................\8 bit parallel adder.v
.......\...\..................\8 bit parallel sub.awf
.......\...\..................\8 bit parallel sub.v
.......\...\..................\8 bit ps using 4 bit ps.awf
.......\...\..................\bcd adder.awf
.......\...\..................\Waveform Editor 2.awf
.......\...\gates\and gate tb.awf
.......\...\.....\and gate.v
.......\...\.....\nand gate tb.awf
.......\...\.....\nand.v
.......\...\.....\nor gate tb.awf
.......\...\.....\nor gate.v
.......\...\.....\not gate tb.awf
.......\...\.....\not gate.v
.......\...\.....\or gate tb.awf
.......\...\.....\or gate.v
.......\...\.....\xnor gate tb.awf
.......\...\.....\xnor gate.v
.......\...\.....\xor gate tb.awf
.......\...\.....\xor gate.v
.......\...\2realization
.......\...\Arithmetic units
.......\...\arithmetic units 2
.......\...\gates
.......\compile
.......\log
.......\src
design0
.......\1.mgf
.......\3.mgf
.......\bde.set
.......\compile\contents.lib~
.......\.......\design0.epr
.......\.......\design0.erf
.......\.......\design0.opt
.......\.......\mega.bin
.......\.......\mega.dbg
.......\.......\mega.elb
.......\.......\mega.itf
.......\.......\mega.mod
.......\.......\mega.off
.......\.......\sources.sth
.......\.......\vcp.mod
.......\.......\vcp.top
.......\.......\wave1.dat
.......\compile.cfg
.......\design0.adf
.......\design0.LIB
.......\design0.wsp
.......\elaboration.log
.......\log\console.log
.......\projlib.cfg
.......\src\2realization\func1.awf
.......\...\............\func1.v
.......\...\............\func2.awf
.......\...\............\func2.v
.......\...\............\func3.awf
.......\...\............\func3.v
.......\...\............\func4.awf
.......\...\............\func4.v
.......\...\Arithmetic units\full adder using half adder.awf
.......\...\................\full adder using half adder.v
.......\...\................\full adder.awf
.......\...\................\full adder.v
.......\...\................\full sub using half sub.awf
.......\...\................\full sub using half sub.v
.......\...\................\full sub.awf
.......\...\................\full sub.v
.......\...\................\haf adder.awf
.......\...\................\half adder.v
.......\...\................\half sub.awf
.......\...\................\half sub.v
.......\...\arithmetic units 2\4 bit bcd adder.v
.......\...\..................\4 bit parallel adder using full adder.v
.......\...\..................\4 bit parallel adder.awf
.......\...\..................\4 bit parallel sub.awf
.......\...\..................\4 bit parallel sub.v
.......\...\..................\8 bit ps using 4 bit ps.v
.......\...\..................\8 bit pa using 4bit pa.awf
.......\...\..................\8 bit parallel adder using 4 bit pa.v
.......\...\..................\8 bit parallel adder.awf
.......\...\..................\8 bit parallel adder.v
.......\...\..................\8 bit parallel sub.awf
.......\...\..................\8 bit parallel sub.v
.......\...\..................\8 bit ps using 4 bit ps.awf
.......\...\..................\bcd adder.awf
.......\...\..................\Waveform Editor 2.awf
.......\...\gates\and gate tb.awf
.......\...\.....\and gate.v
.......\...\.....\nand gate tb.awf
.......\...\.....\nand.v
.......\...\.....\nor gate tb.awf
.......\...\.....\nor gate.v
.......\...\.....\not gate tb.awf
.......\...\.....\not gate.v
.......\...\.....\or gate tb.awf
.......\...\.....\or gate.v
.......\...\.....\xnor gate tb.awf
.......\...\.....\xnor gate.v
.......\...\.....\xor gate tb.awf
.......\...\.....\xor gate.v
.......\...\2realization
.......\...\Arithmetic units
.......\...\arithmetic units 2
.......\...\gates
.......\compile
.......\log
.......\src
design0