文件名称:Chapter4-Sample
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I2C总线和RS- 232串行端口已成为嵌入式系统主要的数据交换接口，可以实现嵌入式系统与外围设备之间的数据传输[2]。但是，在E2PRO里面需要一些I2C总线来写入数据，因为数据技术上的原因，如果没有其他办法，将无法达到所要求的传输速率；同样，对于RS -232串行端口，如果收发程序时处理不当，-I2C-bus and RS-232 serial port has become a major embedded systems for data exchange interfaces, embedded systems and can achieve data transfer between peripheral devices [2]. However, there need some I2C bus E2PRO to write data because the data for technical reasons, if no other way, it will not achieve the required transmission rate Similarly, for the RS-232 serial port, if the sending and receiving treatment program improper
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下载文件列表
Chapter4 Sample\使用说明.txt
...............\I2C\I2C.dhp
...............\...\I2C.npl
...............\...\__projnav.log
...............\...\automake.log
...............\...\coregen.log
...............\...\coregen.prj
...............\...\i2c_master_bit_ctrl.cmd_log
...............\...\i2c_master_bit_ctrl.lso
...............\...\i2c_master_bit_ctrl.ngc
...............\...\i2c_master_bit_ctrl.ngr
...............\...\i2c_master_bit_ctrl.prj
...............\...\i2c_master_bit_ctrl.stx
...............\...\i2c_master_bit_ctrl.syr
...............\...\i2c_master_bit_ctrl.v
...............\...\i2c_master_bit_ctrl.v.bak
...............\...\i2c_master_bit_ctrl_vhdl.prj
...............\...\i2c_master_byte_ctrl.cmd_log
...............\...\i2c_master_byte_ctrl.lso
...............\...\i2c_master_byte_ctrl.ngc
...............\...\i2c_master_byte_ctrl.ngr
...............\...\i2c_master_byte_ctrl.prj
...............\...\i2c_master_byte_ctrl.stx
...............\...\i2c_master_byte_ctrl.syr
...............\...\i2c_master_byte_ctrl.v
...............\...\i2c_master_byte_ctrl.v.bak
...............\...\i2c_master_byte_ctrl_vhdl.prj
...............\...\i2c_master_defines.v
...............\...\i2c_master_defines.v.bak
...............\...\i2c_master_top.cmd_log
...............\...\i2c_master_top.lso
...............\...\i2c_master_top.ngc
...............\...\i2c_master_top.ngr
...............\...\i2c_master_top.prj
...............\...\i2c_master_top.stx
...............\...\i2c_master_top.syr
...............\...\i2c_master_top.v
...............\...\i2c_master_top.v.bak
...............\...\i2c_master_top_vhdl.prj
...............\...\i2c_slave_model.fdo
...............\...\i2c_slave_model.ndo
...............\...\i2c_slave_model.udo
...............\...\i2c_slave_model.v
...............\...\i2c_slave_model.v.bak
...............\...\prjname.lso
...............\...\timescale.v
...............\...\transcript
...............\...\tst_bench_top.v
...............\...\wb_master_model.v
...............\...\wb_master_model.v.bak
...............\...\xst\work\hdllib.ref
...............\...\...\....\vlg67\i2c_master_top.bin
...............\...\...\....\...5C\i2c_master_byte_ctrl.bin
...............\...\...\....\...07\i2c_master_bit_ctrl.bin
...............\...\work\_info
...............\...\....\i2c_slave_model\_primary.dat
...............\...\....\...............\_primary.vhd
...............\...\....\...............\verilog.asm
...............\...\....\glbl\_primary.dat
...............\...\....\....\_primary.vhd
...............\...\....\....\verilog.asm
...............\...\__projnav\I2C.gfl
...............\...\.........\I2C_flowplus.gfl
...............\...\.........\coregen.rsp
...............\...\.........\i2c_master_bit_ctrl.xst
...............\...\.........\i2c_master_byte_ctrl.xst
...............\...\.........\i2c_master_top.xst
...............\...\.........\runXst_tcl.rsp
...............\...\.........\xst_sprjTOstx_tcl.rsp
...............\...\xst\work\vlg67
...............\...\...\....\vlg5C
...............\...\...\....\vlg07
...............\...\...\work
...............\...\work\i2c_slave_model
...............\...\....\glbl
...............\...\xst
...............\...\work
...............\...\__projnav
...............\I2C
Chapter4 Sample
...............\I2C\I2C.dhp
...............\...\I2C.npl
...............\...\__projnav.log
...............\...\automake.log
...............\...\coregen.log
...............\...\coregen.prj
...............\...\i2c_master_bit_ctrl.cmd_log
...............\...\i2c_master_bit_ctrl.lso
...............\...\i2c_master_bit_ctrl.ngc
...............\...\i2c_master_bit_ctrl.ngr
...............\...\i2c_master_bit_ctrl.prj
...............\...\i2c_master_bit_ctrl.stx
...............\...\i2c_master_bit_ctrl.syr
...............\...\i2c_master_bit_ctrl.v
...............\...\i2c_master_bit_ctrl.v.bak
...............\...\i2c_master_bit_ctrl_vhdl.prj
...............\...\i2c_master_byte_ctrl.cmd_log
...............\...\i2c_master_byte_ctrl.lso
...............\...\i2c_master_byte_ctrl.ngc
...............\...\i2c_master_byte_ctrl.ngr
...............\...\i2c_master_byte_ctrl.prj
...............\...\i2c_master_byte_ctrl.stx
...............\...\i2c_master_byte_ctrl.syr
...............\...\i2c_master_byte_ctrl.v
...............\...\i2c_master_byte_ctrl.v.bak
...............\...\i2c_master_byte_ctrl_vhdl.prj
...............\...\i2c_master_defines.v
...............\...\i2c_master_defines.v.bak
...............\...\i2c_master_top.cmd_log
...............\...\i2c_master_top.lso
...............\...\i2c_master_top.ngc
...............\...\i2c_master_top.ngr
...............\...\i2c_master_top.prj
...............\...\i2c_master_top.stx
...............\...\i2c_master_top.syr
...............\...\i2c_master_top.v
...............\...\i2c_master_top.v.bak
...............\...\i2c_master_top_vhdl.prj
...............\...\i2c_slave_model.fdo
...............\...\i2c_slave_model.ndo
...............\...\i2c_slave_model.udo
...............\...\i2c_slave_model.v
...............\...\i2c_slave_model.v.bak
...............\...\prjname.lso
...............\...\timescale.v
...............\...\transcript
...............\...\tst_bench_top.v
...............\...\wb_master_model.v
...............\...\wb_master_model.v.bak
...............\...\xst\work\hdllib.ref
...............\...\...\....\vlg67\i2c_master_top.bin
...............\...\...\....\...5C\i2c_master_byte_ctrl.bin
...............\...\...\....\...07\i2c_master_bit_ctrl.bin
...............\...\work\_info
...............\...\....\i2c_slave_model\_primary.dat
...............\...\....\...............\_primary.vhd
...............\...\....\...............\verilog.asm
...............\...\....\glbl\_primary.dat
...............\...\....\....\_primary.vhd
...............\...\....\....\verilog.asm
...............\...\__projnav\I2C.gfl
...............\...\.........\I2C_flowplus.gfl
...............\...\.........\coregen.rsp
...............\...\.........\i2c_master_bit_ctrl.xst
...............\...\.........\i2c_master_byte_ctrl.xst
...............\...\.........\i2c_master_top.xst
...............\...\.........\runXst_tcl.rsp
...............\...\.........\xst_sprjTOstx_tcl.rsp
...............\...\xst\work\vlg67
...............\...\...\....\vlg5C
...............\...\...\....\vlg07
...............\...\...\work
...............\...\work\i2c_slave_model
...............\...\....\glbl
...............\...\xst
...............\...\work
...............\...\__projnav
...............\I2C
Chapter4 Sample