文件名称:ALUandControl
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用verilogHDL编写的ALU功能实现以及控制信号的产生，还附有波形仿真测试的源文件-Written by verilogHDL ALU function realization and control signal generation, but also with a simulation test of the source waveform
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ALUandControl\ALUandControl_xdb\tmp\ise\__OBJSTORE__\ProjectNavigatorGui\CViewSelector
.............\.................\...\...\............\...................\CViewSelector_StrTbl
.............\.................\...\...\............\................\dpm_project_main\dpm_project_main
.............\.................\...\...\............\................\................\dpm_project_main_StrTbl
.............\.................\...\...\............\................Gui\File-SynthesisOnly
.............\.................\...\...\............\...................\File-SynthesisOnly_StrTbl
.............\.................\...\...\............\xreport\Gc_RvReportViewer-Current-Module
.............\.................\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-AluCtr
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-AluCtr_StrTbl
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-Ctr
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-Ctr_StrTbl
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
.............\.................\...\...\............\HierarchicalDesign\HDProject\HDProject
.............\.................\...\...\............\..................\.........\HDProject_StrTbl
.............\.................\...\...\............\ProjectNavigatorGui\Library-SynthesisOnly
.............\.................\...\...\............\...................\Library-SynthesisOnly_StrTbl
.............\.................\...\...\............\...................\Process-BehavioralSim-
.............\.................\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
.............\.................\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
.............\.................\...\...\............\...................\Process-BehavioralSim-_StrTbl
.............\.................\...\...\............\...................\Process-SynthesisOnly-
.............\.................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
.............\.................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
.............\.................\...\...\............\...................\Process-SynthesisOnly-_StrTbl
.............\.................\...\...\..REGISTRY__\bitgen\regkeys
.............\.................\...\...\............\...init\regkeys
.............\.................\...\...\............\cpldfit\regkeys
.............\.................\...\...\............\dumpngdio\regkeys
.............\.................\...\...\............\XSLTProcess\regkeys
.............\.................\...\...\............\map\regkeys
.............\.................\...\...\............\par\regkeys
.............\.................\...\...\............\xst\regkeys
.............\.................\...\...\............\fuse\regkeys
.............\.................\...\...\............\idem\regkeys
.............\.................\...\...\............\trce\regkeys
.............\.................\...\...\............\.sim\regkeys
.............\.................\...\...\............\xpwr\regkeys
.............\.................\...\...\............\hprep6\regkeys
.............\.................\...\...\............\libgen\regkeys
.............\.................\...\...\............\netgen\regkeys
.............\.................\...\...\............\runner\regkeys
.............\.................\...\...\............\simgen\regkeys
.............\.................\...\...\............\platgen\regkeys
.............\.................\...\...\............\vhpcomp\regkeys
.............\.................\...\...\............\ngc2edif\regkeys
.............\.................\...\
.............\.................\...\...\............\...................\CViewSelector_StrTbl
.............\.................\...\...\............\................\dpm_project_main\dpm_project_main
.............\.................\...\...\............\................\................\dpm_project_main_StrTbl
.............\.................\...\...\............\................Gui\File-SynthesisOnly
.............\.................\...\...\............\...................\File-SynthesisOnly_StrTbl
.............\.................\...\...\............\xreport\Gc_RvReportViewer-Current-Module
.............\.................\...\...\............\.......\Gc_RvReportViewer-Current-Module_StrTbl
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-AluCtr
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-AluCtr_StrTbl
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-Ctr
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-Data-Ctr_StrTbl
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default
.............\.................\...\...\............\.......\Gc_RvReportViewer-Module-DataFactory-Default_StrTbl
.............\.................\...\...\............\HierarchicalDesign\HDProject\HDProject
.............\.................\...\...\............\..................\.........\HDProject_StrTbl
.............\.................\...\...\............\ProjectNavigatorGui\Library-SynthesisOnly
.............\.................\...\...\............\...................\Library-SynthesisOnly_StrTbl
.............\.................\...\...\............\...................\Process-BehavioralSim-
.............\.................\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG
.............\.................\...\...\............\...................\Process-BehavioralSim-DESUT_VERILOG_StrTbl
.............\.................\...\...\............\...................\Process-BehavioralSim-_StrTbl
.............\.................\...\...\............\...................\Process-SynthesisOnly-
.............\.................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG
.............\.................\...\...\............\...................\Process-SynthesisOnly-DESUT_VERILOG_StrTbl
.............\.................\...\...\............\...................\Process-SynthesisOnly-_StrTbl
.............\.................\...\...\..REGISTRY__\bitgen\regkeys
.............\.................\...\...\............\...init\regkeys
.............\.................\...\...\............\cpldfit\regkeys
.............\.................\...\...\............\dumpngdio\regkeys
.............\.................\...\...\............\XSLTProcess\regkeys
.............\.................\...\...\............\map\regkeys
.............\.................\...\...\............\par\regkeys
.............\.................\...\...\............\xst\regkeys
.............\.................\...\...\............\fuse\regkeys
.............\.................\...\...\............\idem\regkeys
.............\.................\...\...\............\trce\regkeys
.............\.................\...\...\............\.sim\regkeys
.............\.................\...\...\............\xpwr\regkeys
.............\.................\...\...\............\hprep6\regkeys
.............\.................\...\...\............\libgen\regkeys
.............\.................\...\...\............\netgen\regkeys
.............\.................\...\...\............\runner\regkeys
.............\.................\...\...\............\simgen\regkeys
.............\.................\...\...\............\platgen\regkeys
.............\.................\...\...\............\vhpcomp\regkeys
.............\.................\...\...\............\ngc2edif\regkeys
.............\.................\...\