文件名称:LIP3001CORE_cpu
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CPU Verilog Module source code
(系统自动生成,下载前可以参看下载内容)
下载文件列表
project_2_impl_1\project_2_impl_1.psi
..........temp_1\analysis.args1.file
................\hdlAnalyze_sysverilogfile
................\hdlAnalyze_verilogfile
................\precision.log
................\precision_rtl.sdc
................\project_2_impl_1.psi
................\sys_con_rep.sdc
................\sys_fsm.rep
................\sys_rtl.ixdb
................\unfolded_blocks.txt
................\rtlc_libs\work\.vextid.map
................\.........\....\2ext0.pkg
................\.........\....\2ext1.pkg
................\.........\....\cheetah_tmp_file
................\.........\....\clk_gate.mod
................\.........\....\clk_gate.mod.body
................\.........\....\main_bus.int
................\.........\....\main_bus.int.body
................\.........\....\rtlc_version_info
................\.....out\.rtlc_compile
................\........\.top
................\........\autotop.conf
................\........\legalmodmap.db
................\........\rtlc.args
................\........\rtlc_args1.file
................\........\vmw.mem_contents
................\........\INCR\emptymod.list
................\........\....\hier.list
................\........\....\incr_driver.log
................\........\....\incr_rtlc.log
................\........\FSM_REPORT\clk_gate.rpt
................\........\..........\sys.rpt
src\cpu.v
...\datapath.v
...\decode.v
...\defines.v
...\lib_fpga.v
...\mem.v
...\memory_board.v
...\mult.v
...\pio.v
...\register.v
...\rom.v
...\sasc_brg.v
...\sasc_fifo4.v
...\sasc_top.v
...\sys.v
...\test.v
...\timescale.v
...\top.v
...\uart.v
...\vdec_dsp16_decode.v
...\vdec_dsp16_regfile.v
..._sv\cpu.sv
......\datapath.sv
......\datapath.v
......\decode.v
......\defines.v
......\lib_fpga.v
......\main_bus.sv
......\mem.v
......\memory_board.sv
......\mult.v
......\pio.sv
......\register.v
......\sasc_brg.v
......\sasc_fifo4.v
......\sasc_top.v
......\sys.sv
......\timescale.v
......\top.sv
......\uart.sv
.jaguarc
precision.log
project_2.psp
setup_datapath.tcl
setup_sys.tcl
setup_top.tcl
project_2_temp_1\rtlc.out\INCR\tmp
................\........\....\AREA
................\...._libs\work
................\.....out\NM
................\........\NET
................\........\MEM
................\........\INCR
................\........\FSM_REPORT
................\........\EXEM_MACRO_DIR
................\........\depend
................\rtlc_libs
................\rtlc.out
project_2_impl_1
project_2_temp_1
src
src_sv
..........temp_1\analysis.args1.file
................\hdlAnalyze_sysverilogfile
................\hdlAnalyze_verilogfile
................\precision.log
................\precision_rtl.sdc
................\project_2_impl_1.psi
................\sys_con_rep.sdc
................\sys_fsm.rep
................\sys_rtl.ixdb
................\unfolded_blocks.txt
................\rtlc_libs\work\.vextid.map
................\.........\....\2ext0.pkg
................\.........\....\2ext1.pkg
................\.........\....\cheetah_tmp_file
................\.........\....\clk_gate.mod
................\.........\....\clk_gate.mod.body
................\.........\....\main_bus.int
................\.........\....\main_bus.int.body
................\.........\....\rtlc_version_info
................\.....out\.rtlc_compile
................\........\.top
................\........\autotop.conf
................\........\legalmodmap.db
................\........\rtlc.args
................\........\rtlc_args1.file
................\........\vmw.mem_contents
................\........\INCR\emptymod.list
................\........\....\hier.list
................\........\....\incr_driver.log
................\........\....\incr_rtlc.log
................\........\FSM_REPORT\clk_gate.rpt
................\........\..........\sys.rpt
src\cpu.v
...\datapath.v
...\decode.v
...\defines.v
...\lib_fpga.v
...\mem.v
...\memory_board.v
...\mult.v
...\pio.v
...\register.v
...\rom.v
...\sasc_brg.v
...\sasc_fifo4.v
...\sasc_top.v
...\sys.v
...\test.v
...\timescale.v
...\top.v
...\uart.v
...\vdec_dsp16_decode.v
...\vdec_dsp16_regfile.v
..._sv\cpu.sv
......\datapath.sv
......\datapath.v
......\decode.v
......\defines.v
......\lib_fpga.v
......\main_bus.sv
......\mem.v
......\memory_board.sv
......\mult.v
......\pio.sv
......\register.v
......\sasc_brg.v
......\sasc_fifo4.v
......\sasc_top.v
......\sys.sv
......\timescale.v
......\top.sv
......\uart.sv
.jaguarc
precision.log
project_2.psp
setup_datapath.tcl
setup_sys.tcl
setup_top.tcl
project_2_temp_1\rtlc.out\INCR\tmp
................\........\....\AREA
................\...._libs\work
................\.....out\NM
................\........\NET
................\........\MEM
................\........\INCR
................\........\FSM_REPORT
................\........\EXEM_MACRO_DIR
................\........\depend
................\rtlc_libs
................\rtlc.out
project_2_impl_1
project_2_temp_1
src
src_sv