文件名称:xapp224_data_recovery_design-file
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XAPP224 VHDL Data Recovery design file
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下载文件列表
xapp224_data_recovery_design file\README.txt
.................................\demo_board\virtex2\vhdl\ucf\top.UCF
.................................\..........\.......\....\...\top_fast.ucf
.................................\..........\.......\....\simulation\tb_top.VHD
.................................\..........\.......\....\..........\tb_top_fast.VHD
.................................\..........\.......\....\..........\top.do
.................................\..........\.......\....\..........\top_fast.do
.................................\..........\.......\....\design_files\data_recovery_virtex2.vhd
.................................\..........\.......\....\............\data_recovery_virtex2_fast.vhd
.................................\..........\.......\....\............\pn23.vhd
.................................\..........\.......\....\............\top.vhd
.................................\..........\.......\....\............\top_fast.vhd
.................................\basic\virtexE\vhdl\ucf\TOP_VE.UCF
.................................\.....\.......\....\simulation\tb_top_ve.vhd
.................................\.....\.......\....\..........\top_ve.do
.................................\.....\.......\....\design_files\data_recovery_virtexe.vhd
.................................\.....\.......\....\............\top_ve.vhd
.................................\.....\.......\.erilog\ucf\TOP_VE.UCF
.................................\.....\.......\.......\simulation\tb_top_ve.v
.................................\.....\.......\.......\..........\top_ve.do
.................................\.....\.......\.......\design_files\data_recovery_virtexe.v
.................................\.....\.......\.......\............\top_ve.v
.................................\.....\......2\vhdl\ucf\TOP_V2.UCF
.................................\.....\.......\....\...\top_v2_fast.ucf
.................................\.....\.......\....\simulation\tb_top_v2.VHD
.................................\.....\.......\....\..........\tb_top_v2_fast.vhd
.................................\.....\.......\....\..........\top_v2.do
.................................\.....\.......\....\..........\top_v2_fast.do
.................................\.....\.......\....\design_files\data_recovery_virtex2.vhd
.................................\.....\.......\....\............\data_recovery_virtex2_fast.vhd
.................................\.....\.......\....\............\top_v2.vhd
.................................\.....\.......\....\............\top_v2_fast.vhd
.................................\.....\.......\.erilog\ucf\TOP_V2.UCF
.................................\.....\.......\.......\...\top_v2_fast.ucf
.................................\.....\.......\.......\simulation\tb_top_v2.v
.................................\.....\.......\.......\..........\tb_top_v2_fast.v
.................................\.....\.......\.......\..........\top_v2.do
.................................\.....\.......\.......\..........\top_v2_fast.do
.................................\.....\.......\.......\design_files\data_recovery_virtex2.v
.................................\.....\.......\.......\............\data_recovery_virtex2_fast.v
.................................\.....\.......\.......\............\top_v2.v
.................................\.....\.......\.......\............\top_v2_fast.v
.................................\demo_board\virtex2\vhdl\ucf
.................................\..........\.......\....\simulation
.................................\..........\.......\....\design_files
.................................\basic\virtexE\vhdl\ucf
.................................\.....\.......\....\simulation
.................................\.....\.......\....\design_files
.................................\.....\.......\.erilog\ucf
.................................\.....\.......\.......\simulation
.................................\.....\.......\.......\design_files
.................................\.....\......2\vhdl\ucf
.................................\.....\.......\....\simulation
.........................
.................................\demo_board\virtex2\vhdl\ucf\top.UCF
.................................\..........\.......\....\...\top_fast.ucf
.................................\..........\.......\....\simulation\tb_top.VHD
.................................\..........\.......\....\..........\tb_top_fast.VHD
.................................\..........\.......\....\..........\top.do
.................................\..........\.......\....\..........\top_fast.do
.................................\..........\.......\....\design_files\data_recovery_virtex2.vhd
.................................\..........\.......\....\............\data_recovery_virtex2_fast.vhd
.................................\..........\.......\....\............\pn23.vhd
.................................\..........\.......\....\............\top.vhd
.................................\..........\.......\....\............\top_fast.vhd
.................................\basic\virtexE\vhdl\ucf\TOP_VE.UCF
.................................\.....\.......\....\simulation\tb_top_ve.vhd
.................................\.....\.......\....\..........\top_ve.do
.................................\.....\.......\....\design_files\data_recovery_virtexe.vhd
.................................\.....\.......\....\............\top_ve.vhd
.................................\.....\.......\.erilog\ucf\TOP_VE.UCF
.................................\.....\.......\.......\simulation\tb_top_ve.v
.................................\.....\.......\.......\..........\top_ve.do
.................................\.....\.......\.......\design_files\data_recovery_virtexe.v
.................................\.....\.......\.......\............\top_ve.v
.................................\.....\......2\vhdl\ucf\TOP_V2.UCF
.................................\.....\.......\....\...\top_v2_fast.ucf
.................................\.....\.......\....\simulation\tb_top_v2.VHD
.................................\.....\.......\....\..........\tb_top_v2_fast.vhd
.................................\.....\.......\....\..........\top_v2.do
.................................\.....\.......\....\..........\top_v2_fast.do
.................................\.....\.......\....\design_files\data_recovery_virtex2.vhd
.................................\.....\.......\....\............\data_recovery_virtex2_fast.vhd
.................................\.....\.......\....\............\top_v2.vhd
.................................\.....\.......\....\............\top_v2_fast.vhd
.................................\.....\.......\.erilog\ucf\TOP_V2.UCF
.................................\.....\.......\.......\...\top_v2_fast.ucf
.................................\.....\.......\.......\simulation\tb_top_v2.v
.................................\.....\.......\.......\..........\tb_top_v2_fast.v
.................................\.....\.......\.......\..........\top_v2.do
.................................\.....\.......\.......\..........\top_v2_fast.do
.................................\.....\.......\.......\design_files\data_recovery_virtex2.v
.................................\.....\.......\.......\............\data_recovery_virtex2_fast.v
.................................\.....\.......\.......\............\top_v2.v
.................................\.....\.......\.......\............\top_v2_fast.v
.................................\demo_board\virtex2\vhdl\ucf
.................................\..........\.......\....\simulation
.................................\..........\.......\....\design_files
.................................\basic\virtexE\vhdl\ucf
.................................\.....\.......\....\simulation
.................................\.....\.......\....\design_files
.................................\.....\.......\.erilog\ucf
.................................\.....\.......\.......\simulation
.................................\.....\.......\.......\design_files
.................................\.....\......2\vhdl\ucf
.................................\.....\.......\....\simulation
.........................