文件名称:7_1LVDS_serilizer
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7:1LVDS编码 为LVDS方面需求的人提供参考设计，很高兴- This VHDL or Verilog source code is intended as a design reference which illustrates how these types of functions can be implemented.
It is the user s responsibility to verify their design for
consistency and functionality through the use of formal
verification methods.
It is the user s responsibility to verify their design for
consistency and functionality through the use of formal
verification methods.
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7_1LVDS_serilizer.txt