文件名称:Group27_lab5
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失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
VHDL的基本门，ram，rom等的实现-VHDL basic door, ram, rom, etc. to achieve
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Group27_lab5
............\Group27_lab5
............\............\lab4(screen_shoot)
............\............\..................\comparator.jpg
............\............\..................\four_bit_syn_counter.jpg
............\............\..................\four_bit_syn_up_down_counter.jpg
............\............\..................\incrementer.jpg
............\............\..................\modulo_counter_with_asyn_reset.jpg
............\............\..................\modulo_counter_with_enable.jpg
............\............\..................\modulo_counter_with_syn_reset.jpg
............\............\..................\nbit_counter_with_load.jpg
............\............\..................\Thumbs.db
............\............\..................\washer_controller.jpg
............\............\lab4(vhdl+ucf)
............\............\..............\automake.log
............\............\..............\d_flipflop.vhd
............\............\..............\d_flipflop_tb.vhd
............\............\..............\eight_bit_comparator.ucf
............\............\..............\eight_bit_comparator.vhd
............\............\..............\eight_bit_compartor_tb.vhd
............\............\..............\eight_bit_modulo_counter_asyn_reset.ucf
............\............\..............\eight_bit_modulo_counter_syn_reset.ucf
............\............\..............\eight_bit_modulo_counter_syn_reset.vhd
............\............\..............\eight_input_nor.vhd
............\............\..............\enable_logic.vhd
............\............\..............\enable_tb.vhd
............\............\..............\four_bit_adder_subtractor.vhd
............\............\..............\four_bit_adder_subtractor_tb.vhd
............\............\..............\four_bit_LAC.vhd
............\............\..............\four_bit_LAC_adder.vhd
............\............\..............\four_bit_reg.vhd
............\............\..............\four_bit_synchronous_counter.ucf
............\............\..............\four_bit_synchronous_counter.vhd
............\............\..............\four_bit_synchronous_counter_tb.vhd
............\............\..............\four_bit_synchronous_up_down_counter.ucf
............\............\..............\four_bit_synchronous_up_down_counter.vhd
............\............\..............\four_bit_synchronous_up_down_counter_tb.vhd
............\............\..............\four_bit_syn_up_down_counter_tb.vhd
............\............\..............\full_adder.vhd
............\............\..............\half_adder.vhd
............\............\..............\lab4.dhp
............\............\..............\lab4.ise
............\............\..............\lab4.ise_ISE_Backup
............\............\..............\modulo_counter_asyn_reset.vhd
............\............\..............\modulo_counter_syn_reset_tb.vhd
............\............\..............\modulo_counter_with_asyn_reset_tb.vhd
............\............\..............\nbit_count_enable.vhd
............\............\..............\nbit_count_enable_tb.vhd
............\............\..............\nbit_incrementer.ucf
............\............\..............\nbit_incrementer.vhd
............\............\..............\nbit_incrementer_tb.vhd
............\............\..............\nbit_reg.ucf
............\............\..............\nbit_reg.vhd
............\............\..............\nbit_reg_tb.vhd
............\............\..............\nbit_reg_timesim.vhd
............\............\..............\nbit_ripple_counter.ucf
............\............\..............\nbit_ripple_counter.vhd
............\............\..............\nbit_ripple_counter_tb.vhd
............\............\..............\nbit_synchronous_counter_with_parallel_load_input.ucf
............\............\..............\nbit_synchronous_counter_with_parallel_load_input.vhd
............\............\..............\nbit_synchronous_counter_with_parallel_load_input_tb.vhd
............\............\..............\nbit_syn_counter_enable.ucf
............\....
............\Group27_lab5
............\............\lab4(screen_shoot)
............\............\..................\comparator.jpg
............\............\..................\four_bit_syn_counter.jpg
............\............\..................\four_bit_syn_up_down_counter.jpg
............\............\..................\incrementer.jpg
............\............\..................\modulo_counter_with_asyn_reset.jpg
............\............\..................\modulo_counter_with_enable.jpg
............\............\..................\modulo_counter_with_syn_reset.jpg
............\............\..................\nbit_counter_with_load.jpg
............\............\..................\Thumbs.db
............\............\..................\washer_controller.jpg
............\............\lab4(vhdl+ucf)
............\............\..............\automake.log
............\............\..............\d_flipflop.vhd
............\............\..............\d_flipflop_tb.vhd
............\............\..............\eight_bit_comparator.ucf
............\............\..............\eight_bit_comparator.vhd
............\............\..............\eight_bit_compartor_tb.vhd
............\............\..............\eight_bit_modulo_counter_asyn_reset.ucf
............\............\..............\eight_bit_modulo_counter_syn_reset.ucf
............\............\..............\eight_bit_modulo_counter_syn_reset.vhd
............\............\..............\eight_input_nor.vhd
............\............\..............\enable_logic.vhd
............\............\..............\enable_tb.vhd
............\............\..............\four_bit_adder_subtractor.vhd
............\............\..............\four_bit_adder_subtractor_tb.vhd
............\............\..............\four_bit_LAC.vhd
............\............\..............\four_bit_LAC_adder.vhd
............\............\..............\four_bit_reg.vhd
............\............\..............\four_bit_synchronous_counter.ucf
............\............\..............\four_bit_synchronous_counter.vhd
............\............\..............\four_bit_synchronous_counter_tb.vhd
............\............\..............\four_bit_synchronous_up_down_counter.ucf
............\............\..............\four_bit_synchronous_up_down_counter.vhd
............\............\..............\four_bit_synchronous_up_down_counter_tb.vhd
............\............\..............\four_bit_syn_up_down_counter_tb.vhd
............\............\..............\full_adder.vhd
............\............\..............\half_adder.vhd
............\............\..............\lab4.dhp
............\............\..............\lab4.ise
............\............\..............\lab4.ise_ISE_Backup
............\............\..............\modulo_counter_asyn_reset.vhd
............\............\..............\modulo_counter_syn_reset_tb.vhd
............\............\..............\modulo_counter_with_asyn_reset_tb.vhd
............\............\..............\nbit_count_enable.vhd
............\............\..............\nbit_count_enable_tb.vhd
............\............\..............\nbit_incrementer.ucf
............\............\..............\nbit_incrementer.vhd
............\............\..............\nbit_incrementer_tb.vhd
............\............\..............\nbit_reg.ucf
............\............\..............\nbit_reg.vhd
............\............\..............\nbit_reg_tb.vhd
............\............\..............\nbit_reg_timesim.vhd
............\............\..............\nbit_ripple_counter.ucf
............\............\..............\nbit_ripple_counter.vhd
............\............\..............\nbit_ripple_counter_tb.vhd
............\............\..............\nbit_synchronous_counter_with_parallel_load_input.ucf
............\............\..............\nbit_synchronous_counter_with_parallel_load_input.vhd
............\............\..............\nbit_synchronous_counter_with_parallel_load_input_tb.vhd
............\............\..............\nbit_syn_counter_enable.ucf
............\....