文件名称:Lab6(result)
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VHDL的小程序，可实现4bits输入的循环-VHDL small procedures, can enter the cycle 4bits
(系统自动生成,下载前可以参看下载内容)
下载文件列表
Lab6(result)\Screenshot\task1.PNG
............\..........\task2.PNG
............\..........\task3.PNG
............\.tate_diagram\task2_state_diagram.pdf
............\.............\Task3_State_Diagram.pdf
............\task1\Controller\controller.vhd
............\.....\..........\d_flipflop.vhd
............\.....\..........\four_input_multiplexer.vhd
............\.....\..........\function_decode_logic.vhd
............\.....\..........\half_adder.vhd
............\.....\..........\nbit_incrementer.vhd
............\.....\..........\nbit_reg.vhd
............\.....\..........\nbit_synchronous_counter_with_parallel_load_input.vhd
............\.....\..........\n_bit_two_input_mux.vhd
............\.....\..........\two_input_multiplexer.vhd
............\.....\datapath\ALU.vhd
............\.....\........\bit_slice.vhd
............\.....\........\datapath.vhd
............\.....\........\d_flipflop.vhd
............\.....\........\eight_n_bit_reg_file.vhd
............\.....\........\four_bit_adder_subtractor.vhd
............\.....\........\four_bit_arithmetric.vhd
............\.....\........\four_bit_LAC.vhd
............\.....\........\four_bit_LAC_adder.vhd
............\.....\........\four_bit_shifter.vhd
............\.....\........\four_input_mux.vhd
............\.....\........\four_input_nor.vhd
............\.....\........\four_input_or_gate.vhd
............\.....\........\full_adder.vhd
............\.....\........\half_adder.vhd
............\.....\........\inverter.vhd
............\.....\........\micro_ones_counter.vhd
............\.....\........\Multiplexer.vhd
............\.....\........\nbit_incrementer.vhd
............\.....\........\nbit_reg.vhd
............\.....\........\nbit_reg_control_triout.vhd
............\.....\........\nbit_reg_with_control.vhd
............\.....\........\nbit_RFC_register.vhd
............\.....\........\nbit_synchronous_counter_with_parallel_load_input.vhd
............\.....\........\nbit_tri_buff.vhd
............\.....\........\nbit_xor_contol.vhd
............\.....\........\n_bit_adder.vhd
............\.....\........\n_bit_logic_unit.vhd
............\.....\........\n_bit_two_input_mux.vhd
............\.....\........\ones_counter_ROM.vhd
............\.....\........\register_file_cell.vhd
............\.....\........\shift_control_logic.vhd
............\.....\........\shift_logic.vhd
............\.....\........\shift_rotate.vhd
............\.....\........\three_input_or.vhd
............\.....\........\three_to_eight_decoder.vhd
............\.....\........\tri_buff.vhd
............\.....\........\two_input_and.vhd
............\.....\........\two_input_and_gate.vhd
............\.....\........\two_input_multiplexer.vhd
............\.....\........\Two_input_mux.vhd
............\.....\........\two_input_nand.vhd
............\.....\........\two_input_nor.vhd
............\.....\........\two_input_or.vhd
............\.....\........\two_input_or_gate.vhd
............\.....\........\two_input_xor.vhd
............\.....\TASK1.ise
............\.....\task1.vhd
............\.....\task1_rom.vhd
............\.....\task1_tb.vhd
............\.....\Testbench\alu_tb.vhd
............\.....\.........\controller_tb.vhd
............\.....\.........\counter_tb.vhd
............\.....\.........\datapath_tb.vhd
............\.....\.........\task3_tb.vhd
............\....2\Controller\controller.vhd
............\.....\..........\d_flipflop.vhd
............\.....\..........\four_input_multiplexer.vhd
............\.....\..........\function_decode_logic.vhd
............\.....\..........\half_adder.vhd
............\.....\..........\nbit_incrementer.vhd
............\.....\..........\nbit_reg.vhd
............\.....\..........\nbit_synchronous_counter_with_parallel_load_input.vhd
............\.....\..........\n_bit_two_input_mux.vhd
............\.....\..........\two_input_multiplexer.vhd
............\.....\datapath\ALU.vhd
............\.....\........\bit_slice.vhd
............\.....\........\datapath.vhd
............\.....\........\d_flipflop.vhd
............\.....\........\eight_n_bit_reg_file.vhd
............\.....\........\four_bit_add
............\..........\task2.PNG
............\..........\task3.PNG
............\.tate_diagram\task2_state_diagram.pdf
............\.............\Task3_State_Diagram.pdf
............\task1\Controller\controller.vhd
............\.....\..........\d_flipflop.vhd
............\.....\..........\four_input_multiplexer.vhd
............\.....\..........\function_decode_logic.vhd
............\.....\..........\half_adder.vhd
............\.....\..........\nbit_incrementer.vhd
............\.....\..........\nbit_reg.vhd
............\.....\..........\nbit_synchronous_counter_with_parallel_load_input.vhd
............\.....\..........\n_bit_two_input_mux.vhd
............\.....\..........\two_input_multiplexer.vhd
............\.....\datapath\ALU.vhd
............\.....\........\bit_slice.vhd
............\.....\........\datapath.vhd
............\.....\........\d_flipflop.vhd
............\.....\........\eight_n_bit_reg_file.vhd
............\.....\........\four_bit_adder_subtractor.vhd
............\.....\........\four_bit_arithmetric.vhd
............\.....\........\four_bit_LAC.vhd
............\.....\........\four_bit_LAC_adder.vhd
............\.....\........\four_bit_shifter.vhd
............\.....\........\four_input_mux.vhd
............\.....\........\four_input_nor.vhd
............\.....\........\four_input_or_gate.vhd
............\.....\........\full_adder.vhd
............\.....\........\half_adder.vhd
............\.....\........\inverter.vhd
............\.....\........\micro_ones_counter.vhd
............\.....\........\Multiplexer.vhd
............\.....\........\nbit_incrementer.vhd
............\.....\........\nbit_reg.vhd
............\.....\........\nbit_reg_control_triout.vhd
............\.....\........\nbit_reg_with_control.vhd
............\.....\........\nbit_RFC_register.vhd
............\.....\........\nbit_synchronous_counter_with_parallel_load_input.vhd
............\.....\........\nbit_tri_buff.vhd
............\.....\........\nbit_xor_contol.vhd
............\.....\........\n_bit_adder.vhd
............\.....\........\n_bit_logic_unit.vhd
............\.....\........\n_bit_two_input_mux.vhd
............\.....\........\ones_counter_ROM.vhd
............\.....\........\register_file_cell.vhd
............\.....\........\shift_control_logic.vhd
............\.....\........\shift_logic.vhd
............\.....\........\shift_rotate.vhd
............\.....\........\three_input_or.vhd
............\.....\........\three_to_eight_decoder.vhd
............\.....\........\tri_buff.vhd
............\.....\........\two_input_and.vhd
............\.....\........\two_input_and_gate.vhd
............\.....\........\two_input_multiplexer.vhd
............\.....\........\Two_input_mux.vhd
............\.....\........\two_input_nand.vhd
............\.....\........\two_input_nor.vhd
............\.....\........\two_input_or.vhd
............\.....\........\two_input_or_gate.vhd
............\.....\........\two_input_xor.vhd
............\.....\TASK1.ise
............\.....\task1.vhd
............\.....\task1_rom.vhd
............\.....\task1_tb.vhd
............\.....\Testbench\alu_tb.vhd
............\.....\.........\controller_tb.vhd
............\.....\.........\counter_tb.vhd
............\.....\.........\datapath_tb.vhd
............\.....\.........\task3_tb.vhd
............\....2\Controller\controller.vhd
............\.....\..........\d_flipflop.vhd
............\.....\..........\four_input_multiplexer.vhd
............\.....\..........\function_decode_logic.vhd
............\.....\..........\half_adder.vhd
............\.....\..........\nbit_incrementer.vhd
............\.....\..........\nbit_reg.vhd
............\.....\..........\nbit_synchronous_counter_with_parallel_load_input.vhd
............\.....\..........\n_bit_two_input_mux.vhd
............\.....\..........\two_input_multiplexer.vhd
............\.....\datapath\ALU.vhd
............\.....\........\bit_slice.vhd
............\.....\........\datapath.vhd
............\.....\........\d_flipflop.vhd
............\.....\........\eight_n_bit_reg_file.vhd
............\.....\........\four_bit_add