文件名称:VGAIPcoreVerilog
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VGA IPcoreVerilog 和不错的代码值得 -VGA IPcoreVerilog
(系统自动生成,下载前可以参看下载内容)
下载文件列表
VGA IPcoreVerilog\VGALCD\b13_safe_09_17_02\auto_baud.v
.................\......\.................\auto_baud_with_tracking.v
.................\......\.................\build_13.ucf
.................\......\.................\clock_divider.v
.................\......\.................\clock_multiply.v
.................\......\.................\reg_4_pack_clrset.v
.................\......\.................\reg_8_pack.v
.................\......\.................\risc16f84_clk2x.v
.................\......\.................\rs232_syscon.v
.................\......\.................\serial.v
.................\......\.................\square_wave_dds.v
.................\......\.................\top.v
.................\......\.................\vga_128_by_92.v
.................\......\.................\xilinx_block_ram_3_3.v
.................\......\.................\xilinx_block_ram_8_16.v
.................\......\b13_safe_09_17_02.zip
.................\......\OPENCORES.files\block_diagram.gif
.................\......\...............\dotty.gif
.................\......\...............\title_logo.gif
.................\......\OPENCORES.htm
.................\......\vga_core.htm
.................\......\vga_core.pdf
.................\......\vga_lcd.htm
.................\......\b13_safe_09_17_02
.................\......\OPENCORES.files
.................\VGALCD
VGA IPcoreVerilog
.................\......\.................\auto_baud_with_tracking.v
.................\......\.................\build_13.ucf
.................\......\.................\clock_divider.v
.................\......\.................\clock_multiply.v
.................\......\.................\reg_4_pack_clrset.v
.................\......\.................\reg_8_pack.v
.................\......\.................\risc16f84_clk2x.v
.................\......\.................\rs232_syscon.v
.................\......\.................\serial.v
.................\......\.................\square_wave_dds.v
.................\......\.................\top.v
.................\......\.................\vga_128_by_92.v
.................\......\.................\xilinx_block_ram_3_3.v
.................\......\.................\xilinx_block_ram_8_16.v
.................\......\b13_safe_09_17_02.zip
.................\......\OPENCORES.files\block_diagram.gif
.................\......\...............\dotty.gif
.................\......\...............\title_logo.gif
.................\......\OPENCORES.htm
.................\......\vga_core.htm
.................\......\vga_core.pdf
.................\......\vga_lcd.htm
.................\......\b13_safe_09_17_02
.................\......\OPENCORES.files
.................\VGALCD
VGA IPcoreVerilog