文件名称:practical_design_verification
- 所属分类：
- VHDL编程
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.9mb
- 下载次数：
- 0次
- 提 供 者：
- sami *****
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- 无
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Improve design efficiency and reduce costs with this practical guide to formal and
simulation-based functional verification. Giving you a theoretical and practical
understanding of the key issues involved, expert authors explain both formal
techniques (model checking and equivalence checking) and simulation-based
techniques (coverage metrics and test generation). You get insights into practical
issues including hardware verification languages (HVLs) and system-level debugging.
The foundations of formal and simulation-based techniques are covered too, as are
more recent research advances including transaction-level modeling and assertionbased
verification, plus the theoretical underpinnings of verification, including the use
of decision diagrams and Boolean satisfiability (SAT).
simulation-based functional verification. Giving you a theoretical and practical
understanding of the key issues involved, expert authors explain both formal
techniques (model checking and equivalence checking) and simulation-based
techniques (coverage metrics and test generation). You get insights into practical
issues including hardware verification languages (HVLs) and system-level debugging.
The foundations of formal and simulation-based techniques are covered too, as are
more recent research advances including transaction-level modeling and assertionbased
verification, plus the theoretical underpinnings of verification, including the use
of decision diagrams and Boolean satisfiability (SAT).
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practical_design_verification.pdf