文件名称:exp_cpu_vhd
- 所属分类：
- VHDL编程
- 资源属性：
- 上传时间：
- 2012-11-26
- 文件大小：
- 2kb
- 下载次数：
- 0次
- 提 供 者：
- doufan******
- 相关连接：
- 无
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- 别用迅雷下载，失败请重下，重下不扣分！
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cpu模型，除了时序和显示模块，有两个warning-A CPU module except downloading parts,such as SHIXU and XIANSHI.This version has 2 warning as below.But functional waveform shows
--a right execution of computing. --ZHANG Hongjie 2010.6.11
-- Warning: Inferred dual-clock RAM node "ram8~17" from synchronous design logic.
-- The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
-- Warning: Inferred dual-clock RAM node "ram8~18" from synchronous design logic.
-- The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
--a right execution of computing. --ZHANG Hongjie 2010.6.11
-- Warning: Inferred dual-clock RAM node "ram8~17" from synchronous design logic.
-- The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
-- Warning: Inferred dual-clock RAM node "ram8~18" from synchronous design logic.
-- The read-during-write behavior of a dual-clock RAM is undefined and may not match the behavior of the original design.
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exp_cpu_vhd.vhd