文件名称:alu4bitsynthesizable
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its a 4 bit arithmetic nd logical unit code in verilog.
the software which is used for it is xilinx
the software which is used for it is xilinx
(系统自动生成,下载前可以参看下载内容)
下载文件列表
alu4bitsynthesizable\alu4bitsynthesizable.dhp
....................\alu4bitsynthesizable.ise
....................\alu4bitsynthesizable.ise_ISE_Backup
....................\au4bitsynthesizable.ldo
....................\au4bitsynthesizable.lso
....................\au4bitsynthesizable.prj
....................\au4bitsynthesizable.stx
....................\au4bitsynthesizable.v
....................\au4bitsynthesizable_vhdl.prj
....................\automake.log
....................\prjname.lso
....................\Project.dhp
....................\transcript
....................\vsim.wlf
....................\wave.do
....................\.ork\au4bitsynthesizable\verilog.psm
....................\....\...................\_primary.dat
....................\....\...................\_primary.vhd
....................\....\comparator\verilog.psm
....................\....\..........\_primary.dat
....................\....\..........\_primary.vhd
....................\....\glbl\verilog.psm
....................\....\....\_primary.dat
....................\....\....\_primary.vhd
....................\....\_info
....................\xst\work\hdllib.ref
....................\...\....\vlg5A\au4bitsynthesizable.bin
....................\...\....\...6C\comparator.bin
....................\__projnav\alu4bitsynthesizable.gfl
....................\.........\alu4bitsynthesizable_flowplus.gfl
....................\.........\au4bitsynthesizable.xst
....................\.........\xst_sprjTOstx_tcl.rsp
....................\__projnav.log
....................\xst\work\vlg5A
....................\...\....\vlg6C
....................\work\au4bitsynthesizable
....................\....\comparator
....................\....\glbl
....................\xst\work
....................\work
....................\xst
....................\_xmsgs
....................\__projnav
alu4bitsynthesizable
....................\alu4bitsynthesizable.ise
....................\alu4bitsynthesizable.ise_ISE_Backup
....................\au4bitsynthesizable.ldo
....................\au4bitsynthesizable.lso
....................\au4bitsynthesizable.prj
....................\au4bitsynthesizable.stx
....................\au4bitsynthesizable.v
....................\au4bitsynthesizable_vhdl.prj
....................\automake.log
....................\prjname.lso
....................\Project.dhp
....................\transcript
....................\vsim.wlf
....................\wave.do
....................\.ork\au4bitsynthesizable\verilog.psm
....................\....\...................\_primary.dat
....................\....\...................\_primary.vhd
....................\....\comparator\verilog.psm
....................\....\..........\_primary.dat
....................\....\..........\_primary.vhd
....................\....\glbl\verilog.psm
....................\....\....\_primary.dat
....................\....\....\_primary.vhd
....................\....\_info
....................\xst\work\hdllib.ref
....................\...\....\vlg5A\au4bitsynthesizable.bin
....................\...\....\...6C\comparator.bin
....................\__projnav\alu4bitsynthesizable.gfl
....................\.........\alu4bitsynthesizable_flowplus.gfl
....................\.........\au4bitsynthesizable.xst
....................\.........\xst_sprjTOstx_tcl.rsp
....................\__projnav.log
....................\xst\work\vlg5A
....................\...\....\vlg6C
....................\work\au4bitsynthesizable
....................\....\comparator
....................\....\glbl
....................\xst\work
....................\work
....................\xst
....................\_xmsgs
....................\__projnav
alu4bitsynthesizable