文件名称:flag
- 所属分类：
- VHDL编程
- 资源属性：
- [PDF]
- 上传时间：
- 2012-11-26
- 文件大小：
- 1.27mb
- 下载次数：
- 0次
- 提 供 者：
- zakirh******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
vga is video graphics
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ALDEC.INI
BTI.INI
ALDEC.LOG
CURRENT.PDF
FLAG.PDF
....\183LIB.ER
....\183LIB.LOG
....\183LIB.V
....\50MHZ_VGA.ER
....\50MHZ_VGA.LOG
....\50MHZ_VGA.V
....\DPM_NET\VGAFLA_G.EDF
....\EXPRESS.INI
....\FLAG.ALB
....\FLAG.BIT
....\FLAG.EDF
....\FLAG.PRJ
....\FLAG.UCF
....\....\CHIPS\VER1\VER1.CST
....\....\.....\....\VER1.RPT
....\....\.....\....\VER1.WS
....\....\.....\....-OPTIMIZED\VER1-OPTIMIZED.CST
....\....\.....\..............\VER1-OPTIMIZED.RPT
....\....\.....\..............\VER1-OPTIMIZED.WS
....\....\FILES\L0.RPT
....\....\.....\L1.RPT
....\....\.....\L2.RPT
....\....\.....\L3.RPT
....\....\FLAG.EXP
....\....\WORKDIRS\WORK\ANAL.INFO
....\....\........\....\ANAL.OUT
....\....\........\....\DFF%VERILOG.SYN
....\....\........\....\DFF%VERILOG__VERILOG.SYN
....\....\........\....\DFF.HNL
....\....\........\....\DFF.MRA
....\....\........\....\DFF.OUT
....\....\........\....\DFF.STS
....\....\........\....\DFF_2.HNL
....\....\........\....\DFF_2.OUT
....\....\........\....\DFF_2.STS
....\....\........\....\DFF_6.HNL
....\....\........\....\DFF_6.OUT
....\....\........\....\DFF_6.STS
....\....\........\....\DFF_8.HNL
....\....\........\....\DFF_8.OUT
....\....\........\....\DFF_8.STS
....\....\........\....\DFFR%VERILOG.SYN
....\....\........\....\DFFR%VERILOG__VERILOG.SYN
....\....\........\....\DFFR.MRA
....\....\........\....\DFFRE%VERILOG.SYN
....\....\........\....\DFFRE%VERILOG__VERILOG.SYN
....\....\........\....\DFFRE.MRA
....\....\........\....\DFFRE_40.HNL
....\....\........\....\DFFRE_40.OUT
....\....\........\....\DFFRE_40.STS
....\....\........\....\SYNC_GEN50%VERILOG.SYN
....\....\........\....\SYNC_GEN50%VERILOG__VERILOG.SYN
....\....\........\....\SYNC_GEN50.HNL
....\....\........\....\SYNC_GEN50.MRA
....\....\........\....\SYNC_GEN50.OUT
....\....\........\....\SYNC_GEN50.STS
....\....\........\....\TCGROM%VERILOG.SYN
....\....\........\....\TCGROM%VERILOG__VERILOG.SYN
....\....\........\....\TCGROM.HNL
....\....\........\....\TCGROM.MRA
....\....\........\....\TCGROM.OUT
....\....\........\....\TCGROM.STS
....\....\........\....\VGAFLA_G%VERILOG.SYN
....\....\........\....\VGAFLA_G%VERILOG__VERILOG.SYN
....\....\........\....\VGAFLA_G.HNL
....\....\........\....\VGAFLA_G.MRA
....\....\........\....\VGAFLA_G.OUT
....\....\........\....\VGAFLA_G.STS
....\FLAG1.SCH
....\LIB\FLAG.BLK
....\...\FLAG.DIR
....\...\FLAG.FIG
....\...\FLAG.FLG
....\...\FLAG.GNR
....\...\FLAG.HDR
....\...\FLAG.ID
....\...\FLAG.INI
....\...\FLAG.MAP
....\...\FLAG.MOD
....\...\FLAG.PIN
....\...\FLAG.SYM
....\...\FLAG.SYN
....\...\FLAG.VIS
....\MOUSE.VHD
....\MOUSE_50MHZ.BAK
....\MOUSE_50MHZ.ER
....\MOUSE_50MHZ.LOG
....\MOUSE_50MHZ.VHD
....\NETLIST.LOG
....\PS2_MOUSE.ER
....\PS2_MOUSE.LOG
....\PS2_MOUSE.V
....\S95.LOG
....\TCGROM.ER
....\TCGROM.LOG
BTI.INI
ALDEC.LOG
CURRENT.PDF
FLAG.PDF
....\183LIB.ER
....\183LIB.LOG
....\183LIB.V
....\50MHZ_VGA.ER
....\50MHZ_VGA.LOG
....\50MHZ_VGA.V
....\DPM_NET\VGAFLA_G.EDF
....\EXPRESS.INI
....\FLAG.ALB
....\FLAG.BIT
....\FLAG.EDF
....\FLAG.PRJ
....\FLAG.UCF
....\....\CHIPS\VER1\VER1.CST
....\....\.....\....\VER1.RPT
....\....\.....\....\VER1.WS
....\....\.....\....-OPTIMIZED\VER1-OPTIMIZED.CST
....\....\.....\..............\VER1-OPTIMIZED.RPT
....\....\.....\..............\VER1-OPTIMIZED.WS
....\....\FILES\L0.RPT
....\....\.....\L1.RPT
....\....\.....\L2.RPT
....\....\.....\L3.RPT
....\....\FLAG.EXP
....\....\WORKDIRS\WORK\ANAL.INFO
....\....\........\....\ANAL.OUT
....\....\........\....\DFF%VERILOG.SYN
....\....\........\....\DFF%VERILOG__VERILOG.SYN
....\....\........\....\DFF.HNL
....\....\........\....\DFF.MRA
....\....\........\....\DFF.OUT
....\....\........\....\DFF.STS
....\....\........\....\DFF_2.HNL
....\....\........\....\DFF_2.OUT
....\....\........\....\DFF_2.STS
....\....\........\....\DFF_6.HNL
....\....\........\....\DFF_6.OUT
....\....\........\....\DFF_6.STS
....\....\........\....\DFF_8.HNL
....\....\........\....\DFF_8.OUT
....\....\........\....\DFF_8.STS
....\....\........\....\DFFR%VERILOG.SYN
....\....\........\....\DFFR%VERILOG__VERILOG.SYN
....\....\........\....\DFFR.MRA
....\....\........\....\DFFRE%VERILOG.SYN
....\....\........\....\DFFRE%VERILOG__VERILOG.SYN
....\....\........\....\DFFRE.MRA
....\....\........\....\DFFRE_40.HNL
....\....\........\....\DFFRE_40.OUT
....\....\........\....\DFFRE_40.STS
....\....\........\....\SYNC_GEN50%VERILOG.SYN
....\....\........\....\SYNC_GEN50%VERILOG__VERILOG.SYN
....\....\........\....\SYNC_GEN50.HNL
....\....\........\....\SYNC_GEN50.MRA
....\....\........\....\SYNC_GEN50.OUT
....\....\........\....\SYNC_GEN50.STS
....\....\........\....\TCGROM%VERILOG.SYN
....\....\........\....\TCGROM%VERILOG__VERILOG.SYN
....\....\........\....\TCGROM.HNL
....\....\........\....\TCGROM.MRA
....\....\........\....\TCGROM.OUT
....\....\........\....\TCGROM.STS
....\....\........\....\VGAFLA_G%VERILOG.SYN
....\....\........\....\VGAFLA_G%VERILOG__VERILOG.SYN
....\....\........\....\VGAFLA_G.HNL
....\....\........\....\VGAFLA_G.MRA
....\....\........\....\VGAFLA_G.OUT
....\....\........\....\VGAFLA_G.STS
....\FLAG1.SCH
....\LIB\FLAG.BLK
....\...\FLAG.DIR
....\...\FLAG.FIG
....\...\FLAG.FLG
....\...\FLAG.GNR
....\...\FLAG.HDR
....\...\FLAG.ID
....\...\FLAG.INI
....\...\FLAG.MAP
....\...\FLAG.MOD
....\...\FLAG.PIN
....\...\FLAG.SYM
....\...\FLAG.SYN
....\...\FLAG.VIS
....\MOUSE.VHD
....\MOUSE_50MHZ.BAK
....\MOUSE_50MHZ.ER
....\MOUSE_50MHZ.LOG
....\MOUSE_50MHZ.VHD
....\NETLIST.LOG
....\PS2_MOUSE.ER
....\PS2_MOUSE.LOG
....\PS2_MOUSE.V
....\S95.LOG
....\TCGROM.ER
....\TCGROM.LOG