文件名称:alu_all
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VHDL设计的流水CPU,开发环境是quartusII,代码经过验证,完全是自主开发的源码-A CPU designed by VHDL with PIPE
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下载文件列表
alu_all\add_16.vhd
.......\alu.vhd
.......\alu2.flow.rpt
.......\alu2.map.rpt
.......\alu2.map.summary
.......\alu2.qpf
.......\alu2.qsf
.......\alu2.qws
.......\alu_all.asm.rpt
.......\alu_all.done
.......\alu_all.eda.rpt
.......\alu_all.fit.eqn
.......\alu_all.fit.rpt
.......\alu_all.fit.summary
.......\alu_all.flow.rpt
.......\alu_all.map.eqn
.......\alu_all.map.rpt
.......\alu_all.map.summary
.......\alu_all.pin
.......\alu_all.pof
.......\alu_all.qpf
.......\alu_all.qsf
.......\alu_all.qws
.......\alu_all.sim.rpt
.......\alu_all.sof
.......\alu_all.tan.rpt
.......\alu_all.tan.summary
.......\alu_all.vhd
.......\alu_all.vhd.bak
.......\alu_all.vwf
.......\cmp_state.ini
.......\db\add_sub_l4h.tdf
.......\..\add_sub_p4h.tdf
.......\..\add_sub_ppg.tdf
.......\..\add_sub_rpg.tdf
.......\..\add_sub_tbf.tdf
.......\..\alu2.cbx.xml
.......\..\alu2.cmp.rdb
.......\..\alu2.db_info
.......\..\alu2.eco.cdb
.......\..\alu2.map.qmsg
.......\..\alu2.sld_design_entry.sci
.......\..\alu2.tis_db_list.ddb
.......\..\alu_all.asm.qmsg
.......\..\alu_all.cbx.xml
.......\..\alu_all.cmp.cdb
.......\..\alu_all.cmp.hdb
.......\..\alu_all.cmp.rdb
.......\..\alu_all.cmp.tdb
.......\..\alu_all.cmp0.ddb
.......\..\alu_all.db_info
.......\..\alu_all.eco.cdb
.......\..\alu_all.eda.qmsg
.......\..\alu_all.eds_overflow
.......\..\alu_all.fit.qmsg
.......\..\alu_all.hier_info
.......\..\alu_all.hif
.......\..\alu_all.map.cdb
.......\..\alu_all.map.hdb
.......\..\alu_all.map.qmsg
.......\..\alu_all.pre_map.cdb
.......\..\alu_all.pre_map.hdb
.......\..\alu_all.psp
.......\..\alu_all.rtlv.hdb
.......\..\alu_all.rtlv_sg.cdb
.......\..\alu_all.rtlv_sg_swap.cdb
.......\..\alu_all.sgdiff.cdb
.......\..\alu_all.sgdiff.hdb
.......\..\alu_all.signalprobe.cdb
.......\..\alu_all.sim.hdb
.......\..\alu_all.sim.qmsg
.......\..\alu_all.sim.rdb
.......\..\alu_all.sim.vwf
.......\..\alu_all.sld_design_entry.sci
.......\..\alu_all.sld_design_entry_dsc.sci
.......\..\alu_all.syn_hier_info
.......\..\alu_all.tan.qmsg
.......\..\alu_all_cmp.qrpt
.......\..\alu_all_sim.qrpt
.......\..\prev_cmp_alu2.map.qmsg
.......\..\prev_cmp_alu2.qmsg
.......\fulladder.vhd
.......\shifter.vhd
.......\.imulation\modelsim\alu_all.vho
.......\..........\........\alu_all_modelsim.xrf
.......\..........\........\alu_all_vhd.sdo
.......\subber.vhd
.......\sub_16.vhd
.......\timing\primetime\alu_all.vho
.......\......\.........\alu_all_pt_vhd.tcl
.......\......\.........\alu_all_vhd.sdo
.......\Vhdl1.vhd
.......\Waveform1.vwf
.......\simulation\modelsim
.......\timing\primetime
.......\db
.......\simulation
.......\timing
alu_all
.......\alu.vhd
.......\alu2.flow.rpt
.......\alu2.map.rpt
.......\alu2.map.summary
.......\alu2.qpf
.......\alu2.qsf
.......\alu2.qws
.......\alu_all.asm.rpt
.......\alu_all.done
.......\alu_all.eda.rpt
.......\alu_all.fit.eqn
.......\alu_all.fit.rpt
.......\alu_all.fit.summary
.......\alu_all.flow.rpt
.......\alu_all.map.eqn
.......\alu_all.map.rpt
.......\alu_all.map.summary
.......\alu_all.pin
.......\alu_all.pof
.......\alu_all.qpf
.......\alu_all.qsf
.......\alu_all.qws
.......\alu_all.sim.rpt
.......\alu_all.sof
.......\alu_all.tan.rpt
.......\alu_all.tan.summary
.......\alu_all.vhd
.......\alu_all.vhd.bak
.......\alu_all.vwf
.......\cmp_state.ini
.......\db\add_sub_l4h.tdf
.......\..\add_sub_p4h.tdf
.......\..\add_sub_ppg.tdf
.......\..\add_sub_rpg.tdf
.......\..\add_sub_tbf.tdf
.......\..\alu2.cbx.xml
.......\..\alu2.cmp.rdb
.......\..\alu2.db_info
.......\..\alu2.eco.cdb
.......\..\alu2.map.qmsg
.......\..\alu2.sld_design_entry.sci
.......\..\alu2.tis_db_list.ddb
.......\..\alu_all.asm.qmsg
.......\..\alu_all.cbx.xml
.......\..\alu_all.cmp.cdb
.......\..\alu_all.cmp.hdb
.......\..\alu_all.cmp.rdb
.......\..\alu_all.cmp.tdb
.......\..\alu_all.cmp0.ddb
.......\..\alu_all.db_info
.......\..\alu_all.eco.cdb
.......\..\alu_all.eda.qmsg
.......\..\alu_all.eds_overflow
.......\..\alu_all.fit.qmsg
.......\..\alu_all.hier_info
.......\..\alu_all.hif
.......\..\alu_all.map.cdb
.......\..\alu_all.map.hdb
.......\..\alu_all.map.qmsg
.......\..\alu_all.pre_map.cdb
.......\..\alu_all.pre_map.hdb
.......\..\alu_all.psp
.......\..\alu_all.rtlv.hdb
.......\..\alu_all.rtlv_sg.cdb
.......\..\alu_all.rtlv_sg_swap.cdb
.......\..\alu_all.sgdiff.cdb
.......\..\alu_all.sgdiff.hdb
.......\..\alu_all.signalprobe.cdb
.......\..\alu_all.sim.hdb
.......\..\alu_all.sim.qmsg
.......\..\alu_all.sim.rdb
.......\..\alu_all.sim.vwf
.......\..\alu_all.sld_design_entry.sci
.......\..\alu_all.sld_design_entry_dsc.sci
.......\..\alu_all.syn_hier_info
.......\..\alu_all.tan.qmsg
.......\..\alu_all_cmp.qrpt
.......\..\alu_all_sim.qrpt
.......\..\prev_cmp_alu2.map.qmsg
.......\..\prev_cmp_alu2.qmsg
.......\fulladder.vhd
.......\shifter.vhd
.......\.imulation\modelsim\alu_all.vho
.......\..........\........\alu_all_modelsim.xrf
.......\..........\........\alu_all_vhd.sdo
.......\subber.vhd
.......\sub_16.vhd
.......\timing\primetime\alu_all.vho
.......\......\.........\alu_all_pt_vhd.tcl
.......\......\.........\alu_all_vhd.sdo
.......\Vhdl1.vhd
.......\Waveform1.vwf
.......\simulation\modelsim
.......\timing\primetime
.......\db
.......\simulation
.......\timing
alu_all