文件名称:fpga_balance_project
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此文件是2009年全国大学生电子设计大赛数字幅频均衡功率放大器的数字部分工程文件，包括modelsim的仿真部分。-This file is the 2009 National Undergraduate Electronic Design Contest figures the number of amplitude-frequency balanced power amplifier part of the project documents, including the modelsim simulation part.
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下载文件列表
fpga_balance_project\modelsim(backup)\balance.v
....................\................\balance.v.bak
....................\................\balance_top.cr.mti
....................\................\balance_top.mpf
....................\................\balance_top.v
....................\................\balance_top.v.bak
....................\................\multiply.v
....................\................\tcl_stacktrace.txt
....................\................\top_balance.xml
....................\................\top_balance_tb.v
....................\................\top_balance_tb.v.bak
....................\................\vsim.wlf
....................\................\work\balance\verilog.asm
....................\................\....\.......\_primary.dat
....................\................\....\.......\_primary.vhd
....................\................\....\multiply\verilog.asm
....................\................\....\........\_primary.dat
....................\................\....\........\_primary.vhd
....................\................\....\top_balance\verilog.asm
....................\................\....\...........\_primary.dat
....................\................\....\...........\_primary.vhd
....................\................\....\..........._tb\verilog.asm
....................\................\....\..............\_primary.dat
....................\................\....\..............\_primary.vhd
....................\................\....\_info
....................\................\....\balance
....................\................\....\multiply
....................\................\....\top_balance
....................\................\....\top_balance_tb
....................\................\work
....................\modelsim(backup)
fpga_balance_project
....................\................\balance.v.bak
....................\................\balance_top.cr.mti
....................\................\balance_top.mpf
....................\................\balance_top.v
....................\................\balance_top.v.bak
....................\................\multiply.v
....................\................\tcl_stacktrace.txt
....................\................\top_balance.xml
....................\................\top_balance_tb.v
....................\................\top_balance_tb.v.bak
....................\................\vsim.wlf
....................\................\work\balance\verilog.asm
....................\................\....\.......\_primary.dat
....................\................\....\.......\_primary.vhd
....................\................\....\multiply\verilog.asm
....................\................\....\........\_primary.dat
....................\................\....\........\_primary.vhd
....................\................\....\top_balance\verilog.asm
....................\................\....\...........\_primary.dat
....................\................\....\...........\_primary.vhd
....................\................\....\..........._tb\verilog.asm
....................\................\....\..............\_primary.dat
....................\................\....\..............\_primary.vhd
....................\................\....\_info
....................\................\....\balance
....................\................\....\multiply
....................\................\....\top_balance
....................\................\....\top_balance_tb
....................\................\work
....................\modelsim(backup)
fpga_balance_project