抢答器在各类竞赛中的必备设备，有单路输入的，也有组输入方式，本设计以FPGA 为基础设计了有三组输入(每组三人)，具有抢答计时控制，能够对各抢答小组成绩进行相应加减操作的通用型抢答器；现行的抢答器中主要有两种：小规模数字逻辑芯片译码器和触发器来做，另外一种用单片机来做；小规模数字逻辑电路比较复杂，用单片机来做随着抢答组数的增加有时候存在I/O 口不足的情况；本设计采用FPGA 来做增强了时序控制的灵活性，同时由于FPGA 的I/O 端口资源丰富，可以在本设计基础上稍加修改可以设计具有多组输入的抢答器。 -Responder in the various competitions of the necessary equipment, a single input, there are group input, the design FPGA-based design has three inputs (three each), with the answer in time control, can the answer in Group results for the corresponding addition and subtraction operation of general-purpose Responder　existing Responder main two: small-scale digital logic chip decoder and the trigger to do, do another with a single chip　small-scale digital logic circuits more complicated to do with the answer in groups with single chip to increase the number of times there I/O port shortage　the design of FPGA to do with increased flexibility in timing control, and because FPGA s I/O port is rich in resources, can be slightly modified on the basis of this design can be designed with multiple input Responder.