文件名称:04z127
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，以可编程逻辑阵列CPLD进行逻辑控制，采用2片现场可
编程门阵列FPGA分别作为图像预处理和2片DSP之间的通信，
实现了实时的基于灰度变换的图像目标识别处理-To programmable logic array CPLD to logic control, with two each field programmable gate array FPGA image preprocessing and communication between two DSP to achieve real-time gray-scale transform-based image recognition processing
编程门阵列FPGA分别作为图像预处理和2片DSP之间的通信，
实现了实时的基于灰度变换的图像目标识别处理-To programmable logic array CPLD to logic control, with two each field programmable gate array FPGA image preprocessing and communication between two DSP to achieve real-time gray-scale transform-based image recognition processing
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04z127.pdf