文件名称:317501408_4_MAC_Spec
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这个是用verilog编写的IPCORE，很有价值，写的相当的不错可以给大家参考-This is written in verilog IPCORE, great value, good writing can give you considerable information
(系统自动生成,下载前可以参看下载内容)
下载文件列表
ethernet
........\sim
........\...\rtl_sim
........\...\.......\src
........\...\.......\...\CVS
........\...\.......\...\...\Root
........\...\.......\...\...\Repository
........\...\.......\...\...\Entries
........\...\.......\run
........\...\.......\...\top_modelsim.do
........\...\.......\...\CVS
........\...\.......\...\...\Root
........\...\.......\...\...\Repository
........\...\.......\...\...\Entries
........\...\.......\ncsim_sim
........\...\.......\.........\CVS
........\...\.......\.........\...\Root
........\...\.......\.........\...\Repository
........\...\.......\.........\...\Entries
........\...\.......\CVS
........\...\.......\...\Root
........\...\.......\...\Repository
........\...\.......\...\Entries
........\...\CVS
........\...\...\Root
........\...\...\Repository
........\...\...\Entries
........\rtl
........\...\verilog
........\...\.......\eth_clockgen.v
........\...\.......\eth_crc.v
........\...\.......\eth_defines.v
........\...\.......\eth_maccontrol.v
........\...\.......\eth_macstatus.v
........\...\.......\eth_miim.v
........\...\.......\eth_outputcontrol.v
........\...\.......\eth_random.v
........\...\.......\eth_receivecontrol.v
........\...\.......\eth_register.v
........\...\.......\eth_registers.v
........\...\.......\eth_rxcounters.v
........\...\.......\eth_rxethmac.v
........\...\.......\eth_rxstatem.v
........\...\.......\eth_shiftreg.v
........\...\.......\eth_sync_clk1_clk2.v
........\...\.......\eth_top.v
........\...\.......\eth_transmitcontrol.v
........\...\.......\eth_txcounters.v
........\...\.......\eth_txethmac.v
........\...\.......\eth_txstatem.v
........\...\.......\eth_wishbonedma.v
........\...\.......\timescale.v
........\...\.......\CVS
........\...\.......\...\Root
........\...\.......\...\Repository
........\...\.......\...\Entries
........\...\CVS
........\...\...\Root
........\...\...\Repository
........\...\...\Entries
........\doc
........\...\eth_speci.pdf
........\...\ethernet_product_brief_OC_head.pdf
........\...\src
........\...\...\eth_speci.doc
........\...\...\ethernet_product_brief.doc
........\...\...\CVS
........\...\...\...\Root
........\...\...\...\Repository
........\...\...\...\Entries
........\...\CVS
........\...\...\Root
........\...\...\Repository
........\...\...\Entries
........\bench
........\.....\verilog
........\.....\.......\tb_eth_top.v
........\.....\.......\CVS
........\.....\.......\...\Root
........\.....\.......\...\Repository
........\.....\.......\...\Entries
........\.....\CVS
........\.....\...\Root
........\.....\...\Repository
........\.....\...\Entries
........\CVS
........\...\Root
........\...\Repository
........\...\Entries
eth_speci.pdf
........\sim
........\...\rtl_sim
........\...\.......\src
........\...\.......\...\CVS
........\...\.......\...\...\Root
........\...\.......\...\...\Repository
........\...\.......\...\...\Entries
........\...\.......\run
........\...\.......\...\top_modelsim.do
........\...\.......\...\CVS
........\...\.......\...\...\Root
........\...\.......\...\...\Repository
........\...\.......\...\...\Entries
........\...\.......\ncsim_sim
........\...\.......\.........\CVS
........\...\.......\.........\...\Root
........\...\.......\.........\...\Repository
........\...\.......\.........\...\Entries
........\...\.......\CVS
........\...\.......\...\Root
........\...\.......\...\Repository
........\...\.......\...\Entries
........\...\CVS
........\...\...\Root
........\...\...\Repository
........\...\...\Entries
........\rtl
........\...\verilog
........\...\.......\eth_clockgen.v
........\...\.......\eth_crc.v
........\...\.......\eth_defines.v
........\...\.......\eth_maccontrol.v
........\...\.......\eth_macstatus.v
........\...\.......\eth_miim.v
........\...\.......\eth_outputcontrol.v
........\...\.......\eth_random.v
........\...\.......\eth_receivecontrol.v
........\...\.......\eth_register.v
........\...\.......\eth_registers.v
........\...\.......\eth_rxcounters.v
........\...\.......\eth_rxethmac.v
........\...\.......\eth_rxstatem.v
........\...\.......\eth_shiftreg.v
........\...\.......\eth_sync_clk1_clk2.v
........\...\.......\eth_top.v
........\...\.......\eth_transmitcontrol.v
........\...\.......\eth_txcounters.v
........\...\.......\eth_txethmac.v
........\...\.......\eth_txstatem.v
........\...\.......\eth_wishbonedma.v
........\...\.......\timescale.v
........\...\.......\CVS
........\...\.......\...\Root
........\...\.......\...\Repository
........\...\.......\...\Entries
........\...\CVS
........\...\...\Root
........\...\...\Repository
........\...\...\Entries
........\doc
........\...\eth_speci.pdf
........\...\ethernet_product_brief_OC_head.pdf
........\...\src
........\...\...\eth_speci.doc
........\...\...\ethernet_product_brief.doc
........\...\...\CVS
........\...\...\...\Root
........\...\...\...\Repository
........\...\...\...\Entries
........\...\CVS
........\...\...\Root
........\...\...\Repository
........\...\...\Entries
........\bench
........\.....\verilog
........\.....\.......\tb_eth_top.v
........\.....\.......\CVS
........\.....\.......\...\Root
........\.....\.......\...\Repository
........\.....\.......\...\Entries
........\.....\CVS
........\.....\...\Root
........\.....\...\Repository
........\.....\...\Entries
........\CVS
........\...\Root
........\...\Repository
........\...\Entries
eth_speci.pdf