文件名称:BER_examination
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基于FPGA的伪随机序列误码率检测，包括随机序列的发生，随机序列的接收统计。-FPGA-based pseudo-random sequence of bit error rate testing, including the occurrence of random sequence, random sequence to receive statistics.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
clock_ctrl\clock_ctrl.qpf
..........\clock_ctrl.qsf
..........\db\cntr_qj7.tdf
..........\..\clock_ctrl.db_info
..........\..\clock_ctrl.cmp.cdb
..........\..\clock_ctrl.tis_db_list.ddb
..........\..\prev_cmp_clock_ctrl.map.qmsg
..........\..\prev_cmp_clock_ctrl.fit.qmsg
..........\..\clock_ctrl.cbx.xml
..........\..\clock_ctrl.map_bb.logdb
..........\..\clock_ctrl.fit.qmsg
..........\..\prev_cmp_clock_ctrl.qmsg
..........\..\clock_ctrl.sim.qmsg
..........\..\clock_ctrl.map.qmsg
..........\..\clock_ctrl.asm.qmsg
..........\..\clock_ctrl.tan.qmsg
..........\..\clock_ctrl.sim.hdb
..........\..\cntr_ejb.tdf
..........\..\clock_ctrl.sim.cvwf
..........\..\prev_cmp_clock_ctrl.sim.qmsg
..........\..\clock_ctrl.sim.rdb
..........\..\clock_ctrl.cmp.logdb
..........\..\mux_03e.tdf
..........\..\clock_ctrl.cmp.ecobp
..........\..\clock_ctrl.cmp_bb.logdb
..........\..\clock_ctrl.eco.cdb
..........\..\clock_ctrl.rtlv.hdb
..........\..\clock_ctrl.pre_map.hdb
..........\..\clock_ctrl.pre_map.cdb
..........\..\prev_cmp_clock_ctrl.asm.qmsg
..........\..\clock_ctrl.sgdiff.cdb
..........\..\clock_ctrl.sgdiff.hdb
..........\..\clock_ctrl.hif
..........\..\prev_cmp_clock_ctrl.tan.qmsg
..........\..\clock_ctrl.hier_info
..........\..\clock_ctrl.rtlv_sg.cdb
..........\..\clock_ctrl.cmp.bpm
..........\..\clock_ctrl.map_bb.cdb
..........\..\clock_ctrl.psp
..........\..\clock_ctrl.dbp
..........\..\clock_ctrl.pss
..........\..\clock_ctrl.syn_hier_info
..........\..\scfifo_5a21.tdf
..........\..\a_dpfifo_cg21.tdf
..........\..\a_fefifo_56f.tdf
..........\..\dpram_mt01.tdf
..........\..\clock_ctrl.map.ecobp
..........\..\altsyncram_krj1.tdf
..........\..\clock_ctrl.map_bb.hdb
..........\..\clock_ctrl.rtlv_sg_swap.cdb
..........\..\clock_ctrl.cmp_bb.rcf
..........\..\clock_ctrl.sld_design_entry.sci
..........\..\clock_ctrl.sld_design_entry_dsc.sci
..........\..\clock_ctrl.map.logdb
..........\..\clock_ctrl.map.cdb
..........\..\clock_ctrl.map.hdb
..........\..\clock_ctrl.map.bpm
..........\..\clock_ctrl.asm_labs.ddb
..........\..\clock_ctrl.signalprobe.cdb
..........\..\clock_ctrl.cmp.tdb
..........\..\clock_ctrl.cmp_bb.hdb
..........\..\clock_ctrl.cmp.hdb
..........\..\clock_ctrl.cmp_bb.cdb
..........\..\clock_ctrl.cmp.rdb
..........\..\clock_ctrl.cmp0.ddb
..........\..\wed.wsf
..........\..\clock_ctrl.eds_overflow
..........\..\add_sub_evh.tdf
..........\clock_ctrl.sim.rpt
..........\clock_ctrl.vhd
..........\clock_ctrl.vhd.bak
..........\clock_ctrl.map.rpt
..........\clock_ctrl.flow.rpt
..........\clock_ctrl.fit.rpt
..........\clock_ctrl.asm.rpt
..........\clock_ctrl.tan.rpt
..........\clock_ctrl.qws
..........\clock_ctrl.map.summary
..........\clock_ctrl.pin
..........\clock_ctrl.fit.smsg
..........\clock_ctrl.fit.summary
..........\clock_ctrl.sof
..........\clock_ctrl.pof
..........\clock_ctrl.tan.summary
..........\clock_ctrl.done
..........\clock_ctrl.vwf
..........\ADDER.vhd.bak
..........\ADDER.vhd
..........\fifo_component.vhd
..........\mux2_1.vhd
..........\fifo.vhd
..........\dff1.vhd
..........\prsg_9.vhd
..........\db
clock_ctrl
..........\sopc_builder_log.txt
..........\clock_ctrl.qsf
..........\db\cntr_qj7.tdf
..........\..\clock_ctrl.db_info
..........\..\clock_ctrl.cmp.cdb
..........\..\clock_ctrl.tis_db_list.ddb
..........\..\prev_cmp_clock_ctrl.map.qmsg
..........\..\prev_cmp_clock_ctrl.fit.qmsg
..........\..\clock_ctrl.cbx.xml
..........\..\clock_ctrl.map_bb.logdb
..........\..\clock_ctrl.fit.qmsg
..........\..\prev_cmp_clock_ctrl.qmsg
..........\..\clock_ctrl.sim.qmsg
..........\..\clock_ctrl.map.qmsg
..........\..\clock_ctrl.asm.qmsg
..........\..\clock_ctrl.tan.qmsg
..........\..\clock_ctrl.sim.hdb
..........\..\cntr_ejb.tdf
..........\..\clock_ctrl.sim.cvwf
..........\..\prev_cmp_clock_ctrl.sim.qmsg
..........\..\clock_ctrl.sim.rdb
..........\..\clock_ctrl.cmp.logdb
..........\..\mux_03e.tdf
..........\..\clock_ctrl.cmp.ecobp
..........\..\clock_ctrl.cmp_bb.logdb
..........\..\clock_ctrl.eco.cdb
..........\..\clock_ctrl.rtlv.hdb
..........\..\clock_ctrl.pre_map.hdb
..........\..\clock_ctrl.pre_map.cdb
..........\..\prev_cmp_clock_ctrl.asm.qmsg
..........\..\clock_ctrl.sgdiff.cdb
..........\..\clock_ctrl.sgdiff.hdb
..........\..\clock_ctrl.hif
..........\..\prev_cmp_clock_ctrl.tan.qmsg
..........\..\clock_ctrl.hier_info
..........\..\clock_ctrl.rtlv_sg.cdb
..........\..\clock_ctrl.cmp.bpm
..........\..\clock_ctrl.map_bb.cdb
..........\..\clock_ctrl.psp
..........\..\clock_ctrl.dbp
..........\..\clock_ctrl.pss
..........\..\clock_ctrl.syn_hier_info
..........\..\scfifo_5a21.tdf
..........\..\a_dpfifo_cg21.tdf
..........\..\a_fefifo_56f.tdf
..........\..\dpram_mt01.tdf
..........\..\clock_ctrl.map.ecobp
..........\..\altsyncram_krj1.tdf
..........\..\clock_ctrl.map_bb.hdb
..........\..\clock_ctrl.rtlv_sg_swap.cdb
..........\..\clock_ctrl.cmp_bb.rcf
..........\..\clock_ctrl.sld_design_entry.sci
..........\..\clock_ctrl.sld_design_entry_dsc.sci
..........\..\clock_ctrl.map.logdb
..........\..\clock_ctrl.map.cdb
..........\..\clock_ctrl.map.hdb
..........\..\clock_ctrl.map.bpm
..........\..\clock_ctrl.asm_labs.ddb
..........\..\clock_ctrl.signalprobe.cdb
..........\..\clock_ctrl.cmp.tdb
..........\..\clock_ctrl.cmp_bb.hdb
..........\..\clock_ctrl.cmp.hdb
..........\..\clock_ctrl.cmp_bb.cdb
..........\..\clock_ctrl.cmp.rdb
..........\..\clock_ctrl.cmp0.ddb
..........\..\wed.wsf
..........\..\clock_ctrl.eds_overflow
..........\..\add_sub_evh.tdf
..........\clock_ctrl.sim.rpt
..........\clock_ctrl.vhd
..........\clock_ctrl.vhd.bak
..........\clock_ctrl.map.rpt
..........\clock_ctrl.flow.rpt
..........\clock_ctrl.fit.rpt
..........\clock_ctrl.asm.rpt
..........\clock_ctrl.tan.rpt
..........\clock_ctrl.qws
..........\clock_ctrl.map.summary
..........\clock_ctrl.pin
..........\clock_ctrl.fit.smsg
..........\clock_ctrl.fit.summary
..........\clock_ctrl.sof
..........\clock_ctrl.pof
..........\clock_ctrl.tan.summary
..........\clock_ctrl.done
..........\clock_ctrl.vwf
..........\ADDER.vhd.bak
..........\ADDER.vhd
..........\fifo_component.vhd
..........\mux2_1.vhd
..........\fifo.vhd
..........\dff1.vhd
..........\prsg_9.vhd
..........\db
clock_ctrl
..........\sopc_builder_log.txt