文件名称:counter999
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采用quartus软件的verilog编程语言编写的计数器模块-Counter module
(系统自动生成,下载前可以参看下载内容)
下载文件列表
计数器999\Block1.bdf
.........\db\jishu0.db_info
.........\..\jishu0.eco.cdb
.........\..\jishu0.sim.vwf
.........\..\jishu0.sld_design_entry.sci
.........\..\wed.zsf
.........\dis.bsf
.........\dis.v
.........\dispselect.bsf
.........\dispselect.inc
.........\dispselect.v
.........\fegpin.v
.........\fen.bsf
.........\fen1hz.bsf
.........\fen1hz.v
.........\fen1k.bsf
.........\fen1k.v
.........\fengpin.bsf
.........\fengpin1.bsf
.........\ji.bsf
.........\jishu0.asm.rpt
.........\jishu0.bsf
.........\jishu0.cdf
.........\jishu0.done
.........\jishu0.dpf
.........\jishu0.fit.rpt
.........\jishu0.fit.smsg
.........\jishu0.fit.summary
.........\jishu0.flow.rpt
.........\jishu0.map.rpt
.........\jishu0.map.smsg
.........\jishu0.map.summary
.........\jishu0.pin
.........\jishu0.pof
.........\jishu0.qpf
.........\jishu0.qsf
.........\jishu0.qws
.........\jishu0.sim.rpt
.........\jishu0.tan.rpt
.........\jishu0.tan.summary
.........\jishu0.vwf
.........\jishu0_assignment_defaults.qdf
.........\jishu1.bsf
.........\jishu1.v
.........\mux.bsf
.........\mux.v
.........\yima.bsf
.........\yima.v
.........\db
计数器999
.........\db\jishu0.db_info
.........\..\jishu0.eco.cdb
.........\..\jishu0.sim.vwf
.........\..\jishu0.sld_design_entry.sci
.........\..\wed.zsf
.........\dis.bsf
.........\dis.v
.........\dispselect.bsf
.........\dispselect.inc
.........\dispselect.v
.........\fegpin.v
.........\fen.bsf
.........\fen1hz.bsf
.........\fen1hz.v
.........\fen1k.bsf
.........\fen1k.v
.........\fengpin.bsf
.........\fengpin1.bsf
.........\ji.bsf
.........\jishu0.asm.rpt
.........\jishu0.bsf
.........\jishu0.cdf
.........\jishu0.done
.........\jishu0.dpf
.........\jishu0.fit.rpt
.........\jishu0.fit.smsg
.........\jishu0.fit.summary
.........\jishu0.flow.rpt
.........\jishu0.map.rpt
.........\jishu0.map.smsg
.........\jishu0.map.summary
.........\jishu0.pin
.........\jishu0.pof
.........\jishu0.qpf
.........\jishu0.qsf
.........\jishu0.qws
.........\jishu0.sim.rpt
.........\jishu0.tan.rpt
.........\jishu0.tan.summary
.........\jishu0.vwf
.........\jishu0_assignment_defaults.qdf
.........\jishu1.bsf
.........\jishu1.v
.........\mux.bsf
.........\mux.v
.........\yima.bsf
.........\yima.v
.........\db
计数器999