文件名称:sdram_verilog
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这是使用VERILOG语言，基于MICRON公司的SDRAM开发的SDRAM接口逻辑-verilog This is the use of language, MICRON-based company's development of the SDRAM SDRAM interface logic
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压缩包 : 7941937sdram_verilog.zip 列表 verilog/ verilog/func_sim/ verilog/func_sim/func_sim.cfg verilog/func_sim/func_sim.log verilog/func_sim/func_sim.vpd verilog/func_sim/run_sim verilog/func_sim/string_decode_fn.v verilog/func_sim/tb_sdrm.v verilog/micron/ verilog/micron/bank0.txt verilog/micron/bank1.txt verilog/micron/mt48lc1m16a1-8a.v verilog/micron/mt48lc1m16a1.v verilog/micron/test.v verilog/par/ verilog/par/run_par verilog/par/sdrm.edf verilog/par/sdrm.ucf verilog/par/sdrm_par.sdf verilog/par/sdrm_par.v verilog/post_route/ verilog/post_route/post_route.cfg verilog/post_route/post_route.log verilog/post_route/post_route.vpd verilog/post_route/run_sim verilog/post_route/sdrm_par.sdf verilog/post_route/sdrm_par.v verilog/post_route/string_decode_post_route.v verilog/post_route/tb_post_route.v verilog/README verilog/src/ verilog/src/brst_cntr.v verilog/src/cslt_cntr.v verilog/src/define.v verilog/src/ki_cntr.v verilog/src/rcd_cntr.v verilog/src/ref_cntr.v verilog/src/sdrm.v verilog/src/sdrmc_state.v verilog/src/sdrm_t.v verilog/src/sys_int.v verilog/synth/ verilog/synth/run_synth verilog/synth/sdrm.edf verilog/synth/sdrm.scr verilog/synth/setup.scr