文件名称:Example
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basic components of vhdl design
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下载文件列表
Examples\FPGA_Optimization\mapping_logic_onto_block_ram\.Xilinx
........\.................\............................\bram_map_1.v
........\.................\............................\bram_map_1.vhd
........\.................\............................\bram_map_2.v
........\.................\............................\bram_map_2.vhd
........\.................\............................\ise\ise.dhp
........\.................\............................\...\ise.ise
........\.................\............................\...\ise.ise_ISE_Backup
........\.................\............................\...\__projnav\runXst_tcl.rsp
........\.................\............................\...\.........\sumrpt_tcl.rsp
........\.................\specifying_inits_and_rlocs_in_hdl_code\inits_rlocs_1.v
........\.................\......................................\inits_rlocs_1.vhd
........\.................\......................................\inits_rlocs_2.v
........\.................\......................................\inits_rlocs_2.vhd
........\.................\......................................\inits_rlocs_3.v
........\.................\......................................\inits_rlocs_3.vhd
........\.................\......................................\.se\ise.dhp
........\.................\......................................\...\ise.ise
........\.................\......................................\...\ise.ise_ISE_Backup
........\.................\......................................\...\v_inits_rlocs_2.xdml
........\.................\......................................\...\v_inits_rlocs_3.xdml
........\.................\......................................\...\__projnav\runXst_tcl.rsp
........\.................\......................................\...\.........\sumrpt_tcl.rsp
........\.................\virtex_primitive_support\ise\ise.dhp
........\.................\........................\...\ise.ise
........\.................\........................\...\ise.ise_ISE_Backup
........\.................\........................\...\__projnav\runXst_tcl.rsp
........\.................\........................\...\.........\sumrpt_tcl.rsp
........\.................\........................\primitive_1.v
........\.................\........................\primitive_1.vhd
........\.................\........................\primitive_2.v
........\.................\........................\primitive_2.vhd
........\.................\........................\primitive_3.v
........\HDL_Coding_Techniques\accumulators\accumulators_1.v
........\.....................\............\accumulators_1.vhd
........\.....................\............\ise\ise.dhp
........\.....................\............\...\ise.ise
........\.....................\............\...\ise.ise_ISE_Backup
........\.....................\............\...\__projnav\runXst_tcl.rsp
........\.....................\............\...\.........\sumrpt_tcl.rsp
........\.....................\.dders\adders_1.v
........\.....................\......\adders_1.vhd
........\.....................\......\adders_2.v
........\.....................\......\adders_2.vhd
........\.....................\......\adders_3.v
........\.....................\......\adders_3.vhd
........\.....................\......\adders_4.v
........\.....................\......\adders_4.vhd
........\.....................\......\adders_5.v
........\.....................\......\adders_5.vhd
........\.....................\......\adders_6.v
........\.....................\......\adders_6.vhd
........\.....................\......\adders_7.v
........\.....................\......\adders_7.vhd
........\.....................\......\ise\ise.dhp
........\.....................\......\...\ise.ise
........\.....................\......\...\ise.ise_ISE_Backup
........\.....................\......\...\__projnav\runXst_tcl.rsp
........\.....................\......\...\.........\sumrpt_tcl.rsp
........\.....................\black_box\black_box_1.v
........\.....................\.........\black_box_1.v
........\.................\............................\bram_map_1.v
........\.................\............................\bram_map_1.vhd
........\.................\............................\bram_map_2.v
........\.................\............................\bram_map_2.vhd
........\.................\............................\ise\ise.dhp
........\.................\............................\...\ise.ise
........\.................\............................\...\ise.ise_ISE_Backup
........\.................\............................\...\__projnav\runXst_tcl.rsp
........\.................\............................\...\.........\sumrpt_tcl.rsp
........\.................\specifying_inits_and_rlocs_in_hdl_code\inits_rlocs_1.v
........\.................\......................................\inits_rlocs_1.vhd
........\.................\......................................\inits_rlocs_2.v
........\.................\......................................\inits_rlocs_2.vhd
........\.................\......................................\inits_rlocs_3.v
........\.................\......................................\inits_rlocs_3.vhd
........\.................\......................................\.se\ise.dhp
........\.................\......................................\...\ise.ise
........\.................\......................................\...\ise.ise_ISE_Backup
........\.................\......................................\...\v_inits_rlocs_2.xdml
........\.................\......................................\...\v_inits_rlocs_3.xdml
........\.................\......................................\...\__projnav\runXst_tcl.rsp
........\.................\......................................\...\.........\sumrpt_tcl.rsp
........\.................\virtex_primitive_support\ise\ise.dhp
........\.................\........................\...\ise.ise
........\.................\........................\...\ise.ise_ISE_Backup
........\.................\........................\...\__projnav\runXst_tcl.rsp
........\.................\........................\...\.........\sumrpt_tcl.rsp
........\.................\........................\primitive_1.v
........\.................\........................\primitive_1.vhd
........\.................\........................\primitive_2.v
........\.................\........................\primitive_2.vhd
........\.................\........................\primitive_3.v
........\HDL_Coding_Techniques\accumulators\accumulators_1.v
........\.....................\............\accumulators_1.vhd
........\.....................\............\ise\ise.dhp
........\.....................\............\...\ise.ise
........\.....................\............\...\ise.ise_ISE_Backup
........\.....................\............\...\__projnav\runXst_tcl.rsp
........\.....................\............\...\.........\sumrpt_tcl.rsp
........\.....................\.dders\adders_1.v
........\.....................\......\adders_1.vhd
........\.....................\......\adders_2.v
........\.....................\......\adders_2.vhd
........\.....................\......\adders_3.v
........\.....................\......\adders_3.vhd
........\.....................\......\adders_4.v
........\.....................\......\adders_4.vhd
........\.....................\......\adders_5.v
........\.....................\......\adders_5.vhd
........\.....................\......\adders_6.v
........\.....................\......\adders_6.vhd
........\.....................\......\adders_7.v
........\.....................\......\adders_7.vhd
........\.....................\......\ise\ise.dhp
........\.....................\......\...\ise.ise
........\.....................\......\...\ise.ise_ISE_Backup
........\.....................\......\...\__projnav\runXst_tcl.rsp
........\.....................\......\...\.........\sumrpt_tcl.rsp
........\.....................\black_box\black_box_1.v
........\.....................\.........\black_box_1.v