文件名称:i2cmmm
- 所属分类：
- VHDL编程
- 资源属性：
- [C/C++] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 500kb
- 下载次数：
- 0次
- 提 供 者：
- zhang******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
i2c 可以直接进行综合-i2c rrrrrrrrrrrrrrrrrrrr
相关搜索： I2C
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c\bench\CVS\Entries
...\.....\...\Repository
...\.....\...\Root
...\.....\verilog\CVS\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\i2c_slave_model.v
...\.....\.......\spi_slave_model.v
...\.....\.......\tst_bench_top.v
...\.....\.......\wb_master_model.v
...\CVS\Entries
...\...\Repository
...\...\Root
...\doc\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c_specs.pdf
...\...\src\CVS\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\I2C_specs.doc
...\...umentation\CVS\Entries
...\.............\...\Repository
...\.............\...\Root
...\rtl\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\verilog\CVS\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\i2c_master_bit_ctrl.v
...\...\.......\i2c_master_byte_ctrl.v
...\...\.......\i2c_master_defines.v
...\...\.......\i2c_master_top.v
...\...\.......\timescale.v
...\...\.hdl\CVS\Entries
...\...\....\...\Repository
...\...\....\...\Root
...\...\....\I2C.VHD
...\...\....\i2c_master_bit_ctrl.vhd
...\...\....\i2c_master_byte_ctrl.vhd
...\...\....\i2c_master_top.vhd
...\...\....\readme
...\...\....\tst_ds1621.vhd
...\sim\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c_verilog\CVS\Entries
...\...\...........\...\Repository
...\...\...........\...\Root
...\...\...........\run\bench.vcd
...\...\...........\...\CVS\Entries
...\...\...........\...\...\Repository
...\...\...........\...\...\Root
...\...\...........\...\INCA_libs\CVS\Entries
...\...\...........\...\.........\...\Repository
...\...\...........\...\.........\...\Root
...\...\...........\...\ncverilog.key
...\...\...........\...\ncverilog.log
...\...\...........\...\run
...\...\...........\...\waves\CVS\Entries
...\...\...........\...\.....\...\Repository
...\...\...........\...\.....\...\Root
...\.oftware\CVS\Entries
...\........\...\Repository
...\........\...\Root
...\........\drivers\CVS\Entries
...\........\.......\...\Repository
...\........\.......\...\Root
...\........\include\CVS\Entries
...\........\.......\...\Repository
...\........\.......\...\Root
...\........\.......\oc_i2c_master.h
...\verilog\CVS\Entries
...\.......\...\Repository
...\.......\...\Root
...\.hdl\CVS\Entries
...\....\...\Repository
...\....\...\Root
...\sim\i2c_verilog\run\INCA_libs\CVS
...\...\...........\...\waves\CVS
...\...\...........\...\CVS
...\...\...........\...\INCA_libs
...\...\...........\...\waves
...\bench\verilog\CVS
...\doc\src\CVS
...\rtl\verilog\CVS
...\...\.hdl\CVS
...\sim\i2c_verilog\CVS
...\...\...........\run
...\.oftware\drivers\CVS
...\........\include\CVS
...\bench\CVS
...\.....\verilog
...\doc\CVS
...\...\src
...\...umentation\CVS
...\rtl\CVS
...\...\verilog
...\...\vhdl
...\.....\...\Repository
...\.....\...\Root
...\.....\verilog\CVS\Entries
...\.....\.......\...\Repository
...\.....\.......\...\Root
...\.....\.......\i2c_slave_model.v
...\.....\.......\spi_slave_model.v
...\.....\.......\tst_bench_top.v
...\.....\.......\wb_master_model.v
...\CVS\Entries
...\...\Repository
...\...\Root
...\doc\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c_specs.pdf
...\...\src\CVS\Entries
...\...\...\...\Repository
...\...\...\...\Root
...\...\...\I2C_specs.doc
...\...umentation\CVS\Entries
...\.............\...\Repository
...\.............\...\Root
...\rtl\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\verilog\CVS\Entries
...\...\.......\...\Repository
...\...\.......\...\Root
...\...\.......\i2c_master_bit_ctrl.v
...\...\.......\i2c_master_byte_ctrl.v
...\...\.......\i2c_master_defines.v
...\...\.......\i2c_master_top.v
...\...\.......\timescale.v
...\...\.hdl\CVS\Entries
...\...\....\...\Repository
...\...\....\...\Root
...\...\....\I2C.VHD
...\...\....\i2c_master_bit_ctrl.vhd
...\...\....\i2c_master_byte_ctrl.vhd
...\...\....\i2c_master_top.vhd
...\...\....\readme
...\...\....\tst_ds1621.vhd
...\sim\CVS\Entries
...\...\...\Repository
...\...\...\Root
...\...\i2c_verilog\CVS\Entries
...\...\...........\...\Repository
...\...\...........\...\Root
...\...\...........\run\bench.vcd
...\...\...........\...\CVS\Entries
...\...\...........\...\...\Repository
...\...\...........\...\...\Root
...\...\...........\...\INCA_libs\CVS\Entries
...\...\...........\...\.........\...\Repository
...\...\...........\...\.........\...\Root
...\...\...........\...\ncverilog.key
...\...\...........\...\ncverilog.log
...\...\...........\...\run
...\...\...........\...\waves\CVS\Entries
...\...\...........\...\.....\...\Repository
...\...\...........\...\.....\...\Root
...\.oftware\CVS\Entries
...\........\...\Repository
...\........\...\Root
...\........\drivers\CVS\Entries
...\........\.......\...\Repository
...\........\.......\...\Root
...\........\include\CVS\Entries
...\........\.......\...\Repository
...\........\.......\...\Root
...\........\.......\oc_i2c_master.h
...\verilog\CVS\Entries
...\.......\...\Repository
...\.......\...\Root
...\.hdl\CVS\Entries
...\....\...\Repository
...\....\...\Root
...\sim\i2c_verilog\run\INCA_libs\CVS
...\...\...........\...\waves\CVS
...\...\...........\...\CVS
...\...\...........\...\INCA_libs
...\...\...........\...\waves
...\bench\verilog\CVS
...\doc\src\CVS
...\rtl\verilog\CVS
...\...\.hdl\CVS
...\sim\i2c_verilog\CVS
...\...\...........\run
...\.oftware\drivers\CVS
...\........\include\CVS
...\bench\CVS
...\.....\verilog
...\doc\CVS
...\...\src
...\...umentation\CVS
...\rtl\CVS
...\...\verilog
...\...\vhdl