用VHDL设计一个四舍五入判别电路，其输入为8421BCD码，要求当输入大于或等于５且小于10时，判别电路输出为１，小于5为０，大于等于10时输出为高阻态。 -VHDL design with a rounded judge circuit, its input 8421BCD code require that when the input is greater than or equal to 5 and less than 10, the discrimination circuit output is 1, less than 5 to 0, greater than or equal 10 outputs high-impedance state .