文件名称:i2c_latest
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介绍说明－－下载内容均来自于网络，请自行研究使用
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of
data exchange between devices.
data exchange between devices.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
i2c_latest\i2c\tags\asyst_2\rtl\verilog\i2c_master_bit_ctrl.v
..........\...\....\.......\...\.......\i2c_master_byte_ctrl.v
..........\...\....\.......\...\.......\i2c_master_defines.v
..........\...\....\.......\...\.......\i2c_master_top.v
..........\...\....\.......\...\.......\timescale.v
..........\...\....\......3\rtl\verilog\i2c_master_bit_ctrl.v
..........\...\....\.......\...\.......\i2c_master_byte_ctrl.v
..........\...\....\.......\...\.......\i2c_master_defines.v
..........\...\....\.......\...\.......\i2c_master_top.v
..........\...\....\.......\...\.......\timescale.v
..........\...\....\first\I2C.VHD
..........\...\....\.....\tst_ds1621.vhd
..........\...\....\rel_1\bench\verilog\i2c_slave_model.v
..........\...\....\.....\.....\.......\tst_bench_top.v
..........\...\....\.....\.....\.......\wb_master_model.v
..........\...\....\.....\doc\i2c_specs.pdf
..........\...\....\.....\...\src\I2C_specs.doc
..........\...\....\.....\rtl\verilog\i2c_master_bit_ctrl.v
..........\...\....\.....\...\.......\i2c_master_byte_ctrl.v
..........\...\....\.....\...\.......\i2c_master_defines.v
..........\...\....\.....\...\.......\i2c_master_top.v
..........\...\....\.....\...\.......\timescale.v
..........\...\....\.....\...\.hdl\I2C.VHD
..........\...\....\.....\...\....\i2c_master_bit_ctrl.vhd
..........\...\....\.....\...\....\i2c_master_byte_ctrl.vhd
..........\...\....\.....\...\....\i2c_master_top.vhd
..........\...\....\.....\...\....\readme
..........\...\....\.....\...\....\tst_ds1621.vhd
..........\...\....\.....\sim\i2c_verilog\run\bench.vcd
..........\...\....\.....\...\...........\...\ncverilog.key
..........\...\....\.....\...\...........\...\ncverilog.log
..........\...\....\.....\...\...........\...\run
..........\...\....\.....\.oftware\include\oc_i2c_master.h
..........\...\.runk\bench\verilog\i2c_slave_model.v
..........\...\.....\.....\.......\spi_slave_model.v
..........\...\.....\.....\.......\tst_bench_top.v
..........\...\.....\.....\.......\wb_master_model.v
..........\...\.....\doc\i2c_specs.pdf
..........\...\.....\...\src\I2C_specs.doc
..........\...\.....\rtl\verilog\i2c_master_bit_ctrl.v
..........\...\.....\...\.......\i2c_master_byte_ctrl.v
..........\...\.....\...\.......\i2c_master_defines.v
..........\...\.....\...\.......\i2c_master_top.v
..........\...\.....\...\.......\timescale.v
..........\...\.....\...\.hdl\I2C.VHD
..........\...\.....\...\....\i2c_master_bit_ctrl.vhd
..........\...\.....\...\....\i2c_master_byte_ctrl.vhd
..........\...\.....\...\....\i2c_master_top.vhd
..........\...\.....\...\....\readme
..........\...\.....\...\....\tst_ds1621.vhd
..........\...\.....\sim\i2c_verilog\run\bench.vcd
..........\...\.....\...\...........\...\ncverilog.key
..........\...\.....\...\...........\...\ncverilog.log
..........\...\.....\...\...........\...\run
..........\...\.....\.oftware\include\oc_i2c_master.h
..........\...\web_uploads\Block.gif
..........\...\...........\i2c_rev03.pdf
..........\...\...........\index.shtml
..........\...\...........\index_orig.shtml
..........\...\tags\rel_1\sim\i2c_verilog\run
..........\...\....\asyst_2\rtl\verilog
..........\...\....\......3\rtl\verilog
..........\...\....\rel_1\bench\verilog
..........\...\....\.....\doc\src
..........\...\....\.....\rtl\verilog
..........\...\....\.....\...\vhdl
..........\...\....\.....\sim\i2c_verilog
..........\...\....\.....\.oftware\include
..........\...\.runk\sim\i2c_verilog\run
..........\...\.ags\asyst_2\rtl
..........\...\....\......3\rtl
..........\...\....\rel_1\bench
..........\...\....\.....\doc
..........\...\....\.....\rtl
..........\...\....\.....\sim
..........\...\....\.....\software
..........\...\.runk\bench\verilog
..........\...\.....\doc\src
..........\...\.....\rtl\verilog
..........\...\.....\...\vhdl
..........\...\.....\sim\i2c_verilog
..........\...\.....\.oftware\include
..........\...\.ags\asyst_2
..........\...\....\asyst_3
..........\...\....\first
..........\...\....\rel_1
..........\...\.runk\bench
..........\...\.....\doc
..........\...\.....\rtl
..........\...\.....\sim
......
..........\...\....\.......\...\.......\i2c_master_byte_ctrl.v
..........\...\....\.......\...\.......\i2c_master_defines.v
..........\...\....\.......\...\.......\i2c_master_top.v
..........\...\....\.......\...\.......\timescale.v
..........\...\....\......3\rtl\verilog\i2c_master_bit_ctrl.v
..........\...\....\.......\...\.......\i2c_master_byte_ctrl.v
..........\...\....\.......\...\.......\i2c_master_defines.v
..........\...\....\.......\...\.......\i2c_master_top.v
..........\...\....\.......\...\.......\timescale.v
..........\...\....\first\I2C.VHD
..........\...\....\.....\tst_ds1621.vhd
..........\...\....\rel_1\bench\verilog\i2c_slave_model.v
..........\...\....\.....\.....\.......\tst_bench_top.v
..........\...\....\.....\.....\.......\wb_master_model.v
..........\...\....\.....\doc\i2c_specs.pdf
..........\...\....\.....\...\src\I2C_specs.doc
..........\...\....\.....\rtl\verilog\i2c_master_bit_ctrl.v
..........\...\....\.....\...\.......\i2c_master_byte_ctrl.v
..........\...\....\.....\...\.......\i2c_master_defines.v
..........\...\....\.....\...\.......\i2c_master_top.v
..........\...\....\.....\...\.......\timescale.v
..........\...\....\.....\...\.hdl\I2C.VHD
..........\...\....\.....\...\....\i2c_master_bit_ctrl.vhd
..........\...\....\.....\...\....\i2c_master_byte_ctrl.vhd
..........\...\....\.....\...\....\i2c_master_top.vhd
..........\...\....\.....\...\....\readme
..........\...\....\.....\...\....\tst_ds1621.vhd
..........\...\....\.....\sim\i2c_verilog\run\bench.vcd
..........\...\....\.....\...\...........\...\ncverilog.key
..........\...\....\.....\...\...........\...\ncverilog.log
..........\...\....\.....\...\...........\...\run
..........\...\....\.....\.oftware\include\oc_i2c_master.h
..........\...\.runk\bench\verilog\i2c_slave_model.v
..........\...\.....\.....\.......\spi_slave_model.v
..........\...\.....\.....\.......\tst_bench_top.v
..........\...\.....\.....\.......\wb_master_model.v
..........\...\.....\doc\i2c_specs.pdf
..........\...\.....\...\src\I2C_specs.doc
..........\...\.....\rtl\verilog\i2c_master_bit_ctrl.v
..........\...\.....\...\.......\i2c_master_byte_ctrl.v
..........\...\.....\...\.......\i2c_master_defines.v
..........\...\.....\...\.......\i2c_master_top.v
..........\...\.....\...\.......\timescale.v
..........\...\.....\...\.hdl\I2C.VHD
..........\...\.....\...\....\i2c_master_bit_ctrl.vhd
..........\...\.....\...\....\i2c_master_byte_ctrl.vhd
..........\...\.....\...\....\i2c_master_top.vhd
..........\...\.....\...\....\readme
..........\...\.....\...\....\tst_ds1621.vhd
..........\...\.....\sim\i2c_verilog\run\bench.vcd
..........\...\.....\...\...........\...\ncverilog.key
..........\...\.....\...\...........\...\ncverilog.log
..........\...\.....\...\...........\...\run
..........\...\.....\.oftware\include\oc_i2c_master.h
..........\...\web_uploads\Block.gif
..........\...\...........\i2c_rev03.pdf
..........\...\...........\index.shtml
..........\...\...........\index_orig.shtml
..........\...\tags\rel_1\sim\i2c_verilog\run
..........\...\....\asyst_2\rtl\verilog
..........\...\....\......3\rtl\verilog
..........\...\....\rel_1\bench\verilog
..........\...\....\.....\doc\src
..........\...\....\.....\rtl\verilog
..........\...\....\.....\...\vhdl
..........\...\....\.....\sim\i2c_verilog
..........\...\....\.....\.oftware\include
..........\...\.runk\sim\i2c_verilog\run
..........\...\.ags\asyst_2\rtl
..........\...\....\......3\rtl
..........\...\....\rel_1\bench
..........\...\....\.....\doc
..........\...\....\.....\rtl
..........\...\....\.....\sim
..........\...\....\.....\software
..........\...\.runk\bench\verilog
..........\...\.....\doc\src
..........\...\.....\rtl\verilog
..........\...\.....\...\vhdl
..........\...\.....\sim\i2c_verilog
..........\...\.....\.oftware\include
..........\...\.ags\asyst_2
..........\...\....\asyst_3
..........\...\....\first
..........\...\....\rel_1
..........\...\.runk\bench
..........\...\.....\doc
..........\...\.....\rtl
..........\...\.....\sim
......