文件名称:74hc85
下载
别用迅雷、360浏览器下载。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
如迅雷强制弹出，可右键点击选“另存为”。
失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
ＩＣ VHDL 集成设计
ＩＣ VHDL 集成设计-ＩＣ VHDL design
ＩＣ VHDL 集成设计-ＩＣ VHDL design
(系统自动生成,下载前可以参看下载内容)
下载文件列表
74hc85.pdf
74hc85
......\74hc85.prj
......\component
......\constraint
......\coreconsole
......\designer
......\........\impl1
......\........\.....\compar4.ide_des
......\........\.....\compare4.adb
......\........\.....\compare4.dtf
......\........\.....\............\verify.log
......\........\.....\compare4.ide_des
......\........\.....\compare4.pdb
......\........\.....\compare4.pdb.depends
......\........\.....\compare4.tcl
......\........\.....\compare4_fp
......\........\.....\...........\$$FlashPro_07294.L$$
......\........\.....\...........\compare4.log
......\........\.....\...........\compare4.pro
......\........\.....\...........\projectData
......\........\.....\...........\...........\compare4.pdb
......\........\.....\designer.log
......\........\.....\simulation
......\hdl
......\...\74hc85.v
......\phy_synthesis
......\simulation
......\..........\modelsim.ini
......\..........\modelsim.ini.sav
......\..........\modelsim.log
......\..........\presynth
......\..........\........\compar4
......\..........\........\.......\verilog.psm
......\..........\........\.......\_primary.dat
......\..........\........\.......\_primary.dbs
......\..........\........\.......\_primary.vhd
......\..........\........\compare4
......\..........\........\........\verilog.psm
......\..........\........\........\_primary.dat
......\..........\........\........\_primary.dbs
......\..........\........\........\_primary.vhd
......\..........\........\testbench
......\..........\........\.........\verilog.psm
......\..........\........\.........\_primary.dat
......\..........\........\.........\_primary.dbs
......\..........\........\.........\_primary.vhd
......\..........\........\_info
......\..........\........\_temp
......\..........\run.do
......\..........\vsim.wlf
......\smartgen
......\........\smartgen.aws
......\stimulus
......\........\testbench.v
......\synthesis
......\.........\.recordref
......\.........\backup
......\.........\compare4.areasrr
......\.........\compare4.edn
......\.........\compare4.fse
......\.........\compare4.htm
......\.........\compare4.map
......\.........\compare4.pdc
......\.........\compare4.sap
......\.........\compare4.sdf
......\.........\compare4.so
......\.........\compare4.srd
......\.........\compare4.srm
......\.........\compare4.srr
......\.........\compare4.srs
......\.........\compare4.szr
......\.........\compare4.tlg
......\.........\compare4_sdc.sdc
......\.........\compare4_syn.prj
......\.........\coreip
......\.........\run_options.txt
......\.........\stdout.log
......\.........\syntmp
......\.........\......\compare4.plg
......\.........\......\compare4_flink.htm
......\.........\......\compare4_srr.htm
......\.........\......\compare4_toc.htm
......\.........\......\sap.log
......\.........\traplog.tlg
......\viewdraw
......\........\sch
......\........\sym
......\........\vf
......\........\..\project.lst
......\........\viewdraw.ini
......\........\wir
74hc85
......\74hc85.prj
......\component
......\constraint
......\coreconsole
......\designer
......\........\impl1
......\........\.....\compar4.ide_des
......\........\.....\compare4.adb
......\........\.....\compare4.dtf
......\........\.....\............\verify.log
......\........\.....\compare4.ide_des
......\........\.....\compare4.pdb
......\........\.....\compare4.pdb.depends
......\........\.....\compare4.tcl
......\........\.....\compare4_fp
......\........\.....\...........\$$FlashPro_07294.L$$
......\........\.....\...........\compare4.log
......\........\.....\...........\compare4.pro
......\........\.....\...........\projectData
......\........\.....\...........\...........\compare4.pdb
......\........\.....\designer.log
......\........\.....\simulation
......\hdl
......\...\74hc85.v
......\phy_synthesis
......\simulation
......\..........\modelsim.ini
......\..........\modelsim.ini.sav
......\..........\modelsim.log
......\..........\presynth
......\..........\........\compar4
......\..........\........\.......\verilog.psm
......\..........\........\.......\_primary.dat
......\..........\........\.......\_primary.dbs
......\..........\........\.......\_primary.vhd
......\..........\........\compare4
......\..........\........\........\verilog.psm
......\..........\........\........\_primary.dat
......\..........\........\........\_primary.dbs
......\..........\........\........\_primary.vhd
......\..........\........\testbench
......\..........\........\.........\verilog.psm
......\..........\........\.........\_primary.dat
......\..........\........\.........\_primary.dbs
......\..........\........\.........\_primary.vhd
......\..........\........\_info
......\..........\........\_temp
......\..........\run.do
......\..........\vsim.wlf
......\smartgen
......\........\smartgen.aws
......\stimulus
......\........\testbench.v
......\synthesis
......\.........\.recordref
......\.........\backup
......\.........\compare4.areasrr
......\.........\compare4.edn
......\.........\compare4.fse
......\.........\compare4.htm
......\.........\compare4.map
......\.........\compare4.pdc
......\.........\compare4.sap
......\.........\compare4.sdf
......\.........\compare4.so
......\.........\compare4.srd
......\.........\compare4.srm
......\.........\compare4.srr
......\.........\compare4.srs
......\.........\compare4.szr
......\.........\compare4.tlg
......\.........\compare4_sdc.sdc
......\.........\compare4_syn.prj
......\.........\coreip
......\.........\run_options.txt
......\.........\stdout.log
......\.........\syntmp
......\.........\......\compare4.plg
......\.........\......\compare4_flink.htm
......\.........\......\compare4_srr.htm
......\.........\......\compare4_toc.htm
......\.........\......\sap.log
......\.........\traplog.tlg
......\viewdraw
......\........\sch
......\........\sym
......\........\vf
......\........\..\project.lst
......\........\viewdraw.ini
......\........\wir