文件名称:QQ
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失败请重下，重下不扣分。
介绍说明－－下载内容均来自于网络，请自行研究使用
这是一个FPGA和pc机之间发送和接收的小程序。-This is an FPGA and pc machines to send and receive between the applets.
(系统自动生成,下载前可以参看下载内容)
下载文件列表
QQ\.lso
..\clock_divider.prj
..\clock_divider.stx
..\clock_divider.vhd
..\clock_divider.xst
..\clock_divider_summary.html
..\clock_divider_vhdl.prj
..\FQQ_summary.html
..\pepExtractor.prj
..\QQ.ise
..\QQ.ise_ISE_Backup
..\QQ.ntrc_log
..\QQ.restore
..\RD_clock.prj
..\RD_clock.stx
..\RD_clock.vhd
..\RD_clock.xst
..\RD_clock_vhdl.prj
..\UART_RX.spl
..\UART_RX.stx
..\UART_RX.sym
..\UART_RX.vhd
..\UART_RX_summary.html
..\UART_TX.cmd_log
..\UART_TX.lso
..\UART_TX.ngc
..\UART_TX.ngr
..\UART_TX.prj
..\UART_TX.stx
..\UART_TX.syr
..\UART_TX.vhd
..\UART_TX.xst
..\UART_TX_summary.html
..\UART_TX_vhdl.prj
..\xst\dump.xst\UART_RX.prj\ntrc.scr
..\...\........\.....TX.prj\ntrc.scr
..\...\work\hdllib.ref
..\...\....\hdpdeps.ref
..\...\....\sub00\vhpl00.vho
..\...\....\.....\vhpl01.vho
..\...\....\.....\vhpl02.vho
..\...\....\.....\vhpl03.vho
..\...\....\.....\vhpl04.vho
..\...\....\.....\vhpl05.vho
..\...\....\.....\vhpl06.vho
..\...\....\.....\vhpl07.vho
..\_xmsgs\xst.xmsgs
..\xst\dump.xst\UART_RX.prj\ngx\notopt
..\...\........\...........\...\opt
..\...\........\.....TX.prj\ngx\notopt
..\...\........\...........\...\opt
..\...\........\.....RX.prj\ngx
..\...\........\.....TX.prj\ngx
..\...\........\UART_RX.prj
..\...\........\UART_TX.prj
..\...\work\sub00
..\...\dump.xst
..\...\file graph
..\...\projnav.tmp
..\...\work
..\xst
..\_xmsgs
QQ
..\clock_divider.prj
..\clock_divider.stx
..\clock_divider.vhd
..\clock_divider.xst
..\clock_divider_summary.html
..\clock_divider_vhdl.prj
..\FQQ_summary.html
..\pepExtractor.prj
..\QQ.ise
..\QQ.ise_ISE_Backup
..\QQ.ntrc_log
..\QQ.restore
..\RD_clock.prj
..\RD_clock.stx
..\RD_clock.vhd
..\RD_clock.xst
..\RD_clock_vhdl.prj
..\UART_RX.spl
..\UART_RX.stx
..\UART_RX.sym
..\UART_RX.vhd
..\UART_RX_summary.html
..\UART_TX.cmd_log
..\UART_TX.lso
..\UART_TX.ngc
..\UART_TX.ngr
..\UART_TX.prj
..\UART_TX.stx
..\UART_TX.syr
..\UART_TX.vhd
..\UART_TX.xst
..\UART_TX_summary.html
..\UART_TX_vhdl.prj
..\xst\dump.xst\UART_RX.prj\ntrc.scr
..\...\........\.....TX.prj\ntrc.scr
..\...\work\hdllib.ref
..\...\....\hdpdeps.ref
..\...\....\sub00\vhpl00.vho
..\...\....\.....\vhpl01.vho
..\...\....\.....\vhpl02.vho
..\...\....\.....\vhpl03.vho
..\...\....\.....\vhpl04.vho
..\...\....\.....\vhpl05.vho
..\...\....\.....\vhpl06.vho
..\...\....\.....\vhpl07.vho
..\_xmsgs\xst.xmsgs
..\xst\dump.xst\UART_RX.prj\ngx\notopt
..\...\........\...........\...\opt
..\...\........\.....TX.prj\ngx\notopt
..\...\........\...........\...\opt
..\...\........\.....RX.prj\ngx
..\...\........\.....TX.prj\ngx
..\...\........\UART_RX.prj
..\...\........\UART_TX.prj
..\...\work\sub00
..\...\dump.xst
..\...\file graph
..\...\projnav.tmp
..\...\work
..\xst
..\_xmsgs