针对全数字软件接收机中抽取滤波器的设计,提出了一种适合在FPGA内实现的单级积分清洗的滤波器结构,这种结构解决了传统积分梳妆滤波器中可能出现的积分器溢出问题,同时还可进行非整数倍的抽取变换.给出了一种无乘法半带滤波器的IIR实现结构,并对该滤波器性能进行了仿真,结果表明在输出过采样率大于4时基本不会影响系统误码性能.-Software for all-digital receiver decimation filter design, presents a suitable FPGA integration within the single-stage cleaning filter structure that points to solve the traditional dressing filters that may arise integrator overflow problem , but can also carry out the extraction of non-integer transform. gives a multiplication-free realization of IIR half-band filter structure and performance of the filter simulation results show that the output sampling rate is greater than 4:00 over the basic will not affect the system BER performance.