文件名称:yiwei2
- 所属分类：
- VHDL编程
- 资源属性：
- 上传时间：
- 2012-11-26
- 文件大小：
- 107kb
- 下载次数：
- 0次
- 提 供 者：
- zhangf******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
16位并行数据转换成串行数据，适用于FPGA与单片几之间的通信问题 （VHDL 编程）-FPGA VHDL
(系统自动生成,下载前可以参看下载内容)
下载文件列表
yiwei2
......\Block1.bdf
......\db
......\..\yiwei.asm.qmsg
......\..\yiwei.asm_labs.ddb
......\..\yiwei.cbx.xml
......\..\yiwei.cmp.cdb
......\..\yiwei.cmp.hdb
......\..\yiwei.cmp.kpt
......\..\yiwei.cmp.logdb
......\..\yiwei.cmp.rdb
......\..\yiwei.cmp.tdb
......\..\yiwei.cmp0.ddb
......\..\yiwei.dbp
......\..\yiwei.db_info
......\..\yiwei.eco.cdb
......\..\yiwei.fit.qmsg
......\..\yiwei.hier_info
......\..\yiwei.hif
......\..\yiwei.map.cdb
......\..\yiwei.map.hdb
......\..\yiwei.map.logdb
......\..\yiwei.map.qmsg
......\..\yiwei.pre_map.cdb
......\..\yiwei.pre_map.hdb
......\..\yiwei.psp
......\..\yiwei.rtlv.hdb
......\..\yiwei.rtlv_sg.cdb
......\..\yiwei.rtlv_sg_swap.cdb
......\..\yiwei.sgdiff.cdb
......\..\yiwei.sgdiff.hdb
......\..\yiwei.signalprobe.cdb
......\..\yiwei.sld_design_entry.sci
......\..\yiwei.sld_design_entry_dsc.sci
......\..\yiwei.syn_hier_info
......\..\yiwei.tan.qmsg
......\rom.bsf
......\rom.cmp
......\rom.vhd
......\yiwei.asm.rpt
......\yiwei.bsf
......\yiwei.done
......\yiwei.fit.rpt
......\yiwei.fit.smsg
......\yiwei.fit.summary
......\yiwei.flow.rpt
......\yiwei.map.rpt
......\yiwei.map.summary
......\yiwei.pin
......\yiwei.pof
......\yiwei.qpf
......\yiwei.qsf
......\yiwei.qws
......\yiwei.sim.rpt
......\yiwei.tan.rpt
......\yiwei.tan.summary
......\yiwei.vhd
......\yiwei.vwf
......\Block1.bdf
......\db
......\..\yiwei.asm.qmsg
......\..\yiwei.asm_labs.ddb
......\..\yiwei.cbx.xml
......\..\yiwei.cmp.cdb
......\..\yiwei.cmp.hdb
......\..\yiwei.cmp.kpt
......\..\yiwei.cmp.logdb
......\..\yiwei.cmp.rdb
......\..\yiwei.cmp.tdb
......\..\yiwei.cmp0.ddb
......\..\yiwei.dbp
......\..\yiwei.db_info
......\..\yiwei.eco.cdb
......\..\yiwei.fit.qmsg
......\..\yiwei.hier_info
......\..\yiwei.hif
......\..\yiwei.map.cdb
......\..\yiwei.map.hdb
......\..\yiwei.map.logdb
......\..\yiwei.map.qmsg
......\..\yiwei.pre_map.cdb
......\..\yiwei.pre_map.hdb
......\..\yiwei.psp
......\..\yiwei.rtlv.hdb
......\..\yiwei.rtlv_sg.cdb
......\..\yiwei.rtlv_sg_swap.cdb
......\..\yiwei.sgdiff.cdb
......\..\yiwei.sgdiff.hdb
......\..\yiwei.signalprobe.cdb
......\..\yiwei.sld_design_entry.sci
......\..\yiwei.sld_design_entry_dsc.sci
......\..\yiwei.syn_hier_info
......\..\yiwei.tan.qmsg
......\rom.bsf
......\rom.cmp
......\rom.vhd
......\yiwei.asm.rpt
......\yiwei.bsf
......\yiwei.done
......\yiwei.fit.rpt
......\yiwei.fit.smsg
......\yiwei.fit.summary
......\yiwei.flow.rpt
......\yiwei.map.rpt
......\yiwei.map.summary
......\yiwei.pin
......\yiwei.pof
......\yiwei.qpf
......\yiwei.qsf
......\yiwei.qws
......\yiwei.sim.rpt
......\yiwei.tan.rpt
......\yiwei.tan.summary
......\yiwei.vhd
......\yiwei.vwf