文件名称:OP07_a
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The OP07 has very low input offset voltage (75 μV max for
OP07E) which is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external nulling.
The OP07 also features low input bias current (±4 nA for
OP07E) and high open-loop gain
OP07E) which is obtained by trimming at the wafer stage. These
low offset voltages generally eliminate any need for external nulling.
The OP07 also features low input bias current (±4 nA for
OP07E) and high open-loop gain
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OP07_a.pdf