文件名称:5Divide
- 所属分类：
- VHDL编程
- 资源属性：
- [VHDL] [源码]
- 上传时间：
- 2012-11-26
- 文件大小：
- 168kb
- 下载次数：
- 0次
- 提 供 者：
- wangf******
- 相关连接：
- 无
- 下载说明：
- 别用迅雷下载，失败请重下，重下不扣分！
介绍说明－－下载内容均来自于网络，请自行研究使用
用Verilog HDL语言写的标准的5分频程序，可以立即使用-Verilog HDL language used to write the standard procedure of 5 min frequency, you can immediately use
(系统自动生成,下载前可以参看下载内容)
下载文件列表
5Divide
.......\#NI.ANI
.......\ani.ani.bat
.......\CLK_3DIV.QSF
.......\clk_5div.asm.rpt
.......\clk_5div.done
.......\clk_5div.fit.eqn
.......\clk_5div.fit.rpt
.......\clk_5div.fit.smsg
.......\clk_5div.fit.summary
.......\clk_5div.flow.rpt
.......\clk_5div.map.eqn
.......\clk_5div.map.rpt
.......\clk_5div.map.summary
.......\CLK_5DIV.PIN
.......\CLK_5DIV.POF
.......\CLK_5DIV.QPF
.......\CLK_5DIV.QSF
.......\CLK_5DIV.QWS
.......\clk_5div.sim.rpt
.......\CLK_5DIV.SOF
.......\clk_5div.tan.rpt
.......\clk_5div.tan.summary
.......\CLK_5DIV.V
.......\CLK_5DIV.VWF
.......\clk_5div_assignment_defaults.qdf
.......\cmp_state.ini
.......\DB
.......\..\#LK_5DIV.HIF
.......\..\#LK_5DIV.PSP
.......\..\clk_3div.eco.cdb
.......\..\clk_3div.sld_design_entry.sci
.......\..\clk_5div.asm.qmsg
.......\..\clk_5div.cbx.xml
.......\..\clk_5div.cmp.cdb
.......\..\clk_5div.cmp.hdb
.......\..\clk_5div.cmp.logdb
.......\..\clk_5div.cmp.rdb
.......\..\clk_5div.cmp.tdb
.......\..\clk_5div.cmp0.ddb
.......\..\CLK_5DIV.DBP
.......\..\clk_5div.db_info
.......\..\clk_5div.eco.cdb
.......\..\clk_5div.eds_overflow
.......\..\clk_5div.fit.qmsg
.......\..\clk_5div.hier_info
.......\..\CLK_5DIV.HIF
.......\..\clk_5div.map.cdb
.......\..\clk_5div.map.hdb
.......\..\clk_5div.map.logdb
.......\..\clk_5div.map.qmsg
.......\..\clk_5div.pre_map.cdb
.......\..\clk_5div.pre_map.hdb
.......\..\CLK_5DIV.PSP
.......\..\CLK_5DIV.PSS
.......\..\clk_5div.rtlv.hdb
.......\..\clk_5div.rtlv_sg.cdb
.......\..\clk_5div.rtlv_sg_swap.cdb
.......\..\clk_5div.rtlv_sg_swap.cdb.wrk
.......\..\clk_5div.sgdiff.cdb
.......\..\clk_5div.sgdiff.hdb
.......\..\clk_5div.signalprobe.cdb
.......\..\clk_5div.signalprobe.cdb.wrk
.......\..\clk_5div.sim.cvwf
.......\..\clk_5div.sim.hdb
.......\..\clk_5div.sim.qmsg
.......\..\clk_5div.sim.rdb
.......\..\clk_5div.sim.vwf
.......\..\clk_5div.sld_design_entry.sci
.......\..\clk_5div.sld_design_entry_dsc.sci
.......\..\clk_5div.syn_hier_info
.......\..\clk_5div.tan.qmsg
.......\..\clk_5div_cmp.qrpt
.......\..\clk_5div_sim.qrpt
.......\..\WED.WSF
.......\#NI.ANI
.......\ani.ani.bat
.......\CLK_3DIV.QSF
.......\clk_5div.asm.rpt
.......\clk_5div.done
.......\clk_5div.fit.eqn
.......\clk_5div.fit.rpt
.......\clk_5div.fit.smsg
.......\clk_5div.fit.summary
.......\clk_5div.flow.rpt
.......\clk_5div.map.eqn
.......\clk_5div.map.rpt
.......\clk_5div.map.summary
.......\CLK_5DIV.PIN
.......\CLK_5DIV.POF
.......\CLK_5DIV.QPF
.......\CLK_5DIV.QSF
.......\CLK_5DIV.QWS
.......\clk_5div.sim.rpt
.......\CLK_5DIV.SOF
.......\clk_5div.tan.rpt
.......\clk_5div.tan.summary
.......\CLK_5DIV.V
.......\CLK_5DIV.VWF
.......\clk_5div_assignment_defaults.qdf
.......\cmp_state.ini
.......\DB
.......\..\#LK_5DIV.HIF
.......\..\#LK_5DIV.PSP
.......\..\clk_3div.eco.cdb
.......\..\clk_3div.sld_design_entry.sci
.......\..\clk_5div.asm.qmsg
.......\..\clk_5div.cbx.xml
.......\..\clk_5div.cmp.cdb
.......\..\clk_5div.cmp.hdb
.......\..\clk_5div.cmp.logdb
.......\..\clk_5div.cmp.rdb
.......\..\clk_5div.cmp.tdb
.......\..\clk_5div.cmp0.ddb
.......\..\CLK_5DIV.DBP
.......\..\clk_5div.db_info
.......\..\clk_5div.eco.cdb
.......\..\clk_5div.eds_overflow
.......\..\clk_5div.fit.qmsg
.......\..\clk_5div.hier_info
.......\..\CLK_5DIV.HIF
.......\..\clk_5div.map.cdb
.......\..\clk_5div.map.hdb
.......\..\clk_5div.map.logdb
.......\..\clk_5div.map.qmsg
.......\..\clk_5div.pre_map.cdb
.......\..\clk_5div.pre_map.hdb
.......\..\CLK_5DIV.PSP
.......\..\CLK_5DIV.PSS
.......\..\clk_5div.rtlv.hdb
.......\..\clk_5div.rtlv_sg.cdb
.......\..\clk_5div.rtlv_sg_swap.cdb
.......\..\clk_5div.rtlv_sg_swap.cdb.wrk
.......\..\clk_5div.sgdiff.cdb
.......\..\clk_5div.sgdiff.hdb
.......\..\clk_5div.signalprobe.cdb
.......\..\clk_5div.signalprobe.cdb.wrk
.......\..\clk_5div.sim.cvwf
.......\..\clk_5div.sim.hdb
.......\..\clk_5div.sim.qmsg
.......\..\clk_5div.sim.rdb
.......\..\clk_5div.sim.vwf
.......\..\clk_5div.sld_design_entry.sci
.......\..\clk_5div.sld_design_entry_dsc.sci
.......\..\clk_5div.syn_hier_info
.......\..\clk_5div.tan.qmsg
.......\..\clk_5div_cmp.qrpt
.......\..\clk_5div_sim.qrpt
.......\..\WED.WSF